ECE 269 VLSI System Testing Krish Chakrabarty Delay Fault Testing 1 Acknowledgment Prof M Tehranipoor University of Connecticut 1 Test Challenges Cost of Manufacturing Test is not scaling ATEs falling further behind device speeds Tester accuracy improves slower than I O speed increases Quality faster product cycles device technologies drive Need for better test methods and coverage Stuck at coverage is no longer sufficient Advanced fault models usable by VLSI design processes Speed and Delay defect coverage are of paramount important 2 1 Test Challenges Cont Power di dt as well as Pave Pmax Need new paradigms for test tooling power supplies Integration of design for power and DFT structural test solutions Increasing Device Integration SOC integrated CPUs Mixed signal plus digital VLSI etc New circuits for MIPs Watt 1V will drive new structural test solutions 3 Advanced Fault Models Stuck at fault model alone is not sufficient for high quality test Open and bridging defects Resistive opens Resistive bridges Transition faults Path delay Opens Cross talk can do a fair amount today still very limited capability Source ITRS 2003 More important on Cu metallization more important moving forward as capacitive coupling increases with lowered Vcc Q per node 4 2 Automatic Test Equipment ATE Automatic Test Equipment ATE Device under test DUT Test Pattern Test Response An Expensive Tester 5 Low Cost Tester IBM and TI are pioneers in designing and using lowcost testers These testers are widely used in their manufacturing test flow Intel uses low cost testers for functional pattern application only NOVTEK Low Cost Tester Efficient delay tests are required for performance 6 verification using low cost testers 3 Delay Test Definition A circuit that passes delay test must produce correct outputs when inputs are applied and outputs observed with specified timing For a combinational or synchronous sequential circuit delay test verifies the limits of delay in combinational logic Delay test problem for asynchronous circuits is complex and not well understood 7 Digital Circuit Timing Input Signal changes Transient region Inputs Output Observation instant Outputs Comb logic Synchronized With clock Clock period time 8 4 Circuit Delays Switching or inertial delay is the interval between input change and output change of a gate Depends on input capacitance device transistor characteristics and output capacitance of gate Also depends on input rise or fall times and states of other inputs secondorder effects Approximation fixed rise and fall delays or min max delay range or single fixed delay for gate output Propagation or interconnect delay is the time a transition takes to travel between gates Depends on transmission line effects distributed R L C parameters length and loading of routing paths Approximation modeled as lumped delays for gate inputs 9 Event Propagation Delays Single lumped inertial delay modeled for each gate PI transitions assumed to occur without time skew Path P1 1 0 13 P2 0 0 2 1 3 246 P3 5 2 10 5 Circuit Outputs Each path can potentially produce one signal transition at the output The location of an output transition in time is determined by the delay of the path Clock period Final value Initial value Fast transitions Slow transitions time Initial value Final value 11 Path Delay Faults PDF Two PDFs rising and falling transitions for each physical path Total number of paths is an exponential function of gates Critical paths identified by static timing analysis e g Primetime from Synopsys must be tested 12 6 Other Delay Fault Models Segment delay fault A segment of an I O path is assumed to have large delay such that all paths containing the segment become faulty Transition fault A segment delay fault with segment of unit length single gate Two faults per gate slow to rise and slow to fall Tests are similar to stuck at fault tests For example a line is initialized to 0 and then tested for s a 0 fault to detect slow to rise transition fault Models spot or gross delay defects Line delay fault A transition fault tested through the longest delay path Two faults per line or gate Tests are dependent on modeled delays of gates Gate delay fault A gate is assumed to have a delay increase of certain amount called fault size while all other gates retain some nominal delays Gate delay faults only of certain sizes may be detectable 13 Slow Clock Test Input latches Combinational circuit Input test clock Test clock period Input test clock Rated clock period Output latches Output test clock Output test clock V2 applied Output latched V1 applied 14 7 Enhanced Scan Test Combinational PO CK circuit SCANOUT CK TC HL HL HOLD HOLD SFF SFF Scanout result V1 settles SCANIN CK TC Scan mode TC CK system clock TC test control HOLD hold signal SFF scan flip flop HL hold latch Normal mode PI CK period Scanin V1 states V1 PI applied Scanin V2 states Result latched V2 PI applied 15 Scan Based Transition Delay Test Transition Test Pattern pair V1 V2 V1 Initialization pattern V2 Launch pattern Capture result SI1 SI2 SIn x SO1 0 1 SO2 SOn Scan based Transition Test Shift in Initialization pattern Launch a transition Capture result Shift out contents Circuit Under Test Launch off Shift LOS and launch off capture LOC are the two most widely used16transition fault test methods 8 Normal Scan Test V2 states generated A by one bit scan shift of V1 or Result latched B by V1 applied in functional mode Combinational CK TC Slow clock SFF TC A SFF CK TC V2 PIs applied Scanin Gen V2 V1 states states circuit SCANOUT V1 PIs applied PO Slow CK period TC B Scan mode Result scanout t Rated CK period Scan mode SCANIN CK system clock TC test control SFF scan flip flop Path tested Normal mode PI Normal mode Scan mode Scan mode 17 Launch off last shift LOS D Q SD SEN CLK V1 01000101 V2 10100010 OR V2 00100010 COMBO LOGIC V1 is applied IC tf V2 is applied LC CC CLK Launch path is scan path more controllable SEN Scan in pattern i Scan out response i 1 Scan in pattern i 1 Scan out response i 18 9 Launch off capture LOC D Q SD SEN CLK COMBO LOGIC IC tf LC CC V2 is applied V1 is applied CLK SEN Scan in pattern i Scan out response i 1 Scan in pattern i 1 Scan out response i Functional launch path Less controllable 19 Variable Clock Sequential Test Off path flip flop PI PI PI PI 0 T1 T n 2 1 PO PI T n 1 T n m PO PO 1 T n 1 1 2 PO PI Tn 2 2 0 D PO PO Initialization sequence slow clock 1 Path activation rated Clock Fault effect propagation sequence