11ECE 269VLSI System TestingKrish ChakrabartyDelay-Fault Testing: 1Acknowledgment: Prof. M. Tehranipoor, University of Connecticut2 Cost of Manufacturing Test is not scaling ATEs falling further behind device speeds Tester accuracy improves slower than I/O speed increases Quality: faster product cycles & device technologies drive Need for better test methods and coverage “Stuck-at” coverage is no longer sufficient Advanced fault models usable by VLSI design processes Speed and Delay defect coverage are of paramount importantTest ChallengesTest Challenges23 Power: di/dt as well as Pave, Pmax Need new paradigms for test tooling, power supplies Integration of design-for-power and DFT/structural test solutions Increasing Device Integration: SOC, integrated CPUs, Mixed signal plus digital VLSI, etc. New circuits for >MIPs/Watt @ 1V will drive new structural test solutionsTest ChallengeTest Challenges (Cont.)s (Cont.)4 Transition faults: can do a fair amount todayPath delay: still very limited capabilityOpens: More important on Cu metallizationCross-talk: more important moving forward as capacitive coupling increases with lowered Vcc, Q per nodeAdvanced Fault ModelsAdvanced Fault ModelsSource: ITRS 2003 Stuck-at fault model alone is not sufficient for high quality test. Open and bridging defects Resistive opens Resistive bridges35Automatic Test Equipment (ATE)Automatic Test Equipment (ATE)Automatic Test Equipment (ATE)Device-under-test (DUT)Test ResponseTest PatternAn Expensive Tester $$$$$$$$$$$$$$$$6LowLow--Cost TeCost Testerster IBM and TI are pioneers in designing and using low-cost testers. These testers are widely used in their manufacturing test flow. Intel uses low-cost testers for functional pattern application only.NOVTEK Low-Cost Tester Efficient delay tests are required for performance verification using low-cost testers.47Delay Test DefinitionDelay Test Definition• A circuit that passes delay test must produce correct outputs when inputs are applied and outputs observed with specified timing.• For a combinational or synchronous sequential circuit, delay test verifies the limits of delay in combinational logic.• Delay test problem for asynchronous circuits is complex and not well understood.8Digital Circuit TimingDigital Circuit TimingInputSignalchangesInputsOutputstimeTransientregionClock periodComb.logicOutputObservationinstantSynchronizedWith clock59Circuit DelaysCircuit Delays• Switching or inertial delay is the interval between input change and output change of a gate:Depends on input capacitance, device (transistor) characteristics and output capacitance of gate. Also depends on input rise or fall times and states of other inputs (second-order effects). Approximation: fixed rise and fall delays (or min-max delay range, or single fixed delay) for gate output.• Propagation or interconnect delay is the time a transition takes to travel between gates:Depends on transmission line effects (distributed R, L, C parameters, length and loading) of routing paths. Approximation: modeled as lumped delays for gate inputs.10Event Propagation DelaysEvent Propagation Delays2 4 611 353100022Path P1P2P3Single lumped inertial delay modeled for each gatePI transitions assumed to occur without time skew611Circuit OutputsCircuit Outputs• Each path can potentially produce one signal transition at the output.• The location of an output transition in time is determined by the delay of the path.Initial valueInitial valueFinal valueFinal valueClock periodFast transitionsSlow transitionstime12PathPath--Delay Faults (PDF)Delay Faults (PDF)• Two PDFs (rising and falling transitions) for each physical path.• Total number of paths is an exponential function of gates. Critical paths, identified by static timing analysis (e.g., Primetimefrom Synopsys), must be tested.713Other Delay Fault ModelsOther Delay Fault Models• Segment-delay fault -- A segment of an I/O path is assumed to have large delay such that all paths containing the segment become faulty.• Transition fault -- A segment-delay fault with segment of unit length (single gate):Two faults per gate; slow-to-rise and slow-to-fall. Tests are similar to stuck-at fault tests. For example, a line is initialized to 0 and then tested for s-a-0 fault to detect slow-to-rise transition fault. Models spot (or gross) delay defects.• Line-delay fault – A transition fault tested through the longest delay path. Two faults per line or gate. Tests are dependent on modeled delays of gates.• Gate-delay fault – A gate is assumed to have a delay increase of certain amount (called fault size) while all other gates retain some nominal delays. Gate-delay faults only of certain sizes may be detectable.14SlowSlow--Clock TestClock TestInputtest clockOutputtest clockCombinationalcircuitInputlatchesOutputlatchesInputtest clockOutputtest clockV1appliedV2appliedOutputlatchedTestclockperiodRatedclockperiod815EnhancedEnhanced--Scan TestScan TestCombinationalcircuitHLSFFHLSFFPIPOSCANINSCAN-OUTHOLDCK TCCK TCCK: system clockTC: test controlHOLD: hold signalSFF: scan flip-flopHL: hold latchCKHOLDCKperiodNormalmodeTCScan modeV1 PIappliedV2 PIappliedScaninV1statesScaninV2 statesV1 settlesResultlatchedScanoutresult16 Transition Test Pattern pair (V1, V2) V1 – Initialization pattern V2 – Launch pattern Capture result Scan-based Transition Test Shift-in (Initialization pattern) Launch a transition Capture result Shift-out contentsScanScan--Based Transition Delay TestBased Transition Delay Testx0→1………SI1SI2SO1SO2Launch-off-Shift (LOS) and launch-off-capture (LOC) are the two most widely used transition fault test methods.Circuit Under Test……SInSOn917NormalNormal--Scan TestScan TestCombinationalcircuitSFFSFFPIPOSCANINSCAN-OUTCK TCCK TCCK: system clockTC: test controlSFF: scan flip-flopRatedCK periodNormalmodeTC(A)Scan modeV1 PIsappliedV2 PIsappliedScaninV1 statesResultlatchedResultscanoutV2 states generated, (A) by one-bit scan shift of V1, or(B) by V1 applied in functional mode.Scan modeNormal modeTC(B)Scan modeScan modeSlow CKperiodtGen. V2statesPathtestedSlow clock18LaunchLaunch--offoff--lastlast--shift (LOS)shift (LOS) Launch path is scan path, more controllableV1= 01000101V2= 10100010V2= 00100010OR…Scan−in pattern iScan−out response i−1Scan−in pattern i+1Scan−out
View Full Document