INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS 2009 EDITION TEST AND TEST EQUIPMENT THE ITRS IS DEVISED AND INTENDED FOR TECHNOLOGY ASSESSMENT ONLY AND IS WITHOUT REGARD TO ANY COMMERCIAL CONSIDERATIONS PERTAINING TO INDIVIDUAL PRODUCTS OR EQUIPMENT.THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2009 EDITION TABLE OF CONTENTS Introduction and Scope of the 2009 edition .....................................................................................1 Key Drivers, Difficult Challenges, and Future Opportunities............................................................1 Key Drivers...................................................................................................................................................4 Difficult Challenges (in priority order)...........................................................................................................7 Future Opportunities ....................................................................................................................................9 Test and Yield Learning.................................................................................................................10 Electrical-Test -Based Diagnosis ...............................................................................................................10 Failure Analysis..........................................................................................................................................11 Test Cost Focus Topic...................................................................................................................12 Base Cost Trend ........................................................................................................................................14 Channel Cost Trend...................................................................................................................................14 Power Cost Trend ......................................................................................................................................15 Interface Cost Trend ..................................................................................................................................15 Multi-site Trend ..........................................................................................................................................15 Other Cost Trends......................................................................................................................................16 Important Areas of Concern.......................................................................................................................16 Adaptive Test ..........................................................................................................................17 Adaptive Test definition..............................................................................................................................17 Process Variability – its impact on Testing ................................................................................................18 Directions for Adaptive Test in the next 5–10 years ..................................................................................19 Adaptive Test Building Blocks....................................................................................................................20 Test Technology Requirements.....................................................................................................21 Introduction ................................................................................................................................................21 System Integration—SoC and SiP Test Challenges and Implications ......................................................22 Logic...........................................................................................................................................................28 High Speed Input/Output Interface ............................................................................................................29 Memory ......................................................................................................................................................34 Analog and Mixed-signal............................................................................................................................35 Radio Frequency........................................................................................................................................36 Reliability Technology Requirements ............................................................................................37 Burn-In Requirements................................................................................................................................38 Test Mechanical Handling Requirements......................................................................................40 Device Interface Technology Requirements..................................................................................41 Probe Cards...............................................................................................................................................42 Test Sockets ..............................................................................................................................................45 Specialty Devices ..........................................................................................................................48LIST OF FIGURES Figure TST1 Test Cost Drivers..............................................................................................12 Figure TST2 Test Cell Cost / Unit versus Interface Cost Trend ............................................14 Figure TST3 Importance of Multi-site Efficiency in Massive Parallel Test.............................16 Figure TST4 High-level diagram of Adaptive Test Flow........................................................18 Figure TST5 Organization of Cores for System Integration and Applications.......................22 Figure TST6 Potential Solution for the Problem of the Test Data Increase...........................23 Figure TST7 Impact of Repeated Use of Same Cores..........................................................24 Figure TST8 Potential Solutions for Test Time Reduction
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