INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS 2009 EDITION TEST AND TEST EQUIPMENT THE ITRS IS DEVISED AND INTENDED FOR TECHNOLOGY ASSESSMENT ONLY AND IS WITHOUT REGARD TO ANY COMMERCIAL CONSIDERATIONS PERTAINING TO INDIVIDUAL PRODUCTS OR EQUIPMENT TABLE OF CONTENTS Introduction and Scope of the 2009 edition 1 Key Drivers Difficult Challenges and Future Opportunities 1 Key Drivers 4 Difficult Challenges in priority order 7 Future Opportunities 9 Test and Yield Learning 10 Electrical Test Based Diagnosis 10 Failure Analysis 11 Test Cost Focus Topic 12 Base Cost Trend 14 Channel Cost Trend 14 Power Cost Trend 15 Interface Cost Trend 15 Multi site Trend 15 Other Cost Trends 16 Important Areas of Concern 16 Adaptive Test 17 Adaptive Test definition 17 Process Variability its impact on Testing 18 Directions for Adaptive Test in the next 5 10 years 19 Adaptive Test Building Blocks 20 Test Technology Requirements 21 Introduction 21 System Integration SoC and SiP Test Challenges and Implications 22 Logic 28 High Speed Input Output Interface 29 Memory 34 Analog and Mixed signal 35 Radio Frequency 36 Reliability Technology Requirements 37 Burn In Requirements 38 Test Mechanical Handling Requirements 40 Device Interface Technology Requirements 41 Probe Cards 42 Test Sockets 45 Specialty Devices 48 THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS 2009 EDITION LIST OF FIGURES Figure TST1 Figure TST2 Figure TST3 Figure TST4 Figure TST5 Figure TST6 Figure TST7 Figure TST8 Figure TST9 Figure TST10 Figure TST11 Figure TST12 Figure TST13 Figure TST14 Test Cost Drivers 12 Test Cell Cost Unit versus Interface Cost Trend 14 Importance of Multi site Efficiency in Massive Parallel Test 16 High level diagram of Adaptive Test Flow 18 Organization of Cores for System Integration and Applications 22 Potential Solution for the Problem of the Test Data Increase 23 Impact of Repeated Use of Same Cores 24 Potential Solutions for Test Time Reduction 24 High Speed Interface Trend 30 High Speed I O Jitter Test Accuracy Requirements Scaling with Frequency 33 The Production Process with WLBI Compared with Package Burn in 39 Probing and Wirebond Contacting a Bond Pad 44 Contactor Types 47 Image Sensor Cell 49 LIST OF TABLES Table TST1 Table TST2 Table TST3 Table TST4 Table TST5 Table TST6 Table TST7 Table TST8 Table TST9 Table TST10 Table TST11 Table TST12 Table TST13 Table TST14 Table TST15 Table TST16 Table TST17 Summary of Key Test Drivers Challenges and Opportunities 3 Multi site Test for Product Segments 15 Stages of Adaptive Test 19 Implications of Adaptive Test 21 System on Chip Test Requirements 24 Logic Test Requirements 29 Vector Multipliers 29 Memory Test Requirements 34 Mixed signal Test Requirements 36 RF Test Requirements 36 Burn In Test Requirements 39 Test Handler and Prober Difficult Challenges 41 Prober Requirements 41 Handler Requirements 41 Probing Difficult Challenges 43 Wafer Probe Technology Requirements 45 Test Socket Technology Requirements 48 THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS 2009 EDITION Test and Test Equipment 1 TEST AND TEST EQUIPMENT INTRODUCTION AND SCOPE OF THE 2009 EDITION The 2009 edition of the Test Roadmap contains some significant changes to many of the tables includes a new section on Adaptive Test includes some discussion of 3D silicon devices and added accelerometers to the Specialty Devices section A survey on Cost of Test was completed in 2009 and the results are included in the Cost of Test Focus topic section The high speed interfaces section was heavily updated Other sections of the chapter contain only minor revisions Adaptive test has been being adopted as a method to reduce overall product test cost and improve product yields The Test chapter now devotes an entire section to adaptive test concepts challenges impact to engineering and factory methodology IT infrastructure requirements and some implementation examples 3D Three Dimensional silicon devices have been added to the key drivers for 2009 The concept of 3D devices is that a single design is implemented across multiple die connected by TSVs Thru Silicon Vias in order to optimize the cost and performance of devices The SoC methodology of integrating a very complex system on a single chip can require many mask layers to be added to a technology to accommodate the requirements of the SoC The 3D concept allows each die domain to be process optimized i e Logic DRAM NVM Analog but introduces design and test complexities The test parallelism table has remained controversial even though new device categories have been added since 2005 so typical functional pin count assumptions have been added as notes However as many devices are being tested at wafer probe using reduce pin interfaces all possible parallelisms cannot be included in the table The SoC table has been revised to reflect the latest trends and the chapter section has been appropriately changed Formulas based changes in the Logic Table reflect the impact of the 2009 MPU and Consumer transistor count changes in the ORTC tables Memory changes were also driven by the 2009 ORTC density roadmap Carrier frequency range in the RF table has been broken into general and special radio categories and the rapid increase in modulation bandwidth required for technologies such as UWB has moved out in time The remainder of the table reflects small changes in numeric values and some cell color changes Prober probecard handlers and test socket tables have had significant changes The prober table has had a near complete rewrite so changes are not easily summarized Probecards now reflect a special LCD display driver probe requirements section to specify the unique challenges of testing these devices Handlers broke the high power 10W device requirements into a med hi 10 50W range and a high range 50W Test sockets now covers blade rubber contacts and also included a table showing socket self inductance must be reduced below 0 3nH to properly support 6GHz and below 0 1nH for support of 20GHz signals There were either no changes or only cell color changes or small numerical changes to the Vector multiplier Mixed signal Burn in and Probing difficult challenges tables This document represents significant contributions from a large number of participants representing a wide cross section of the industry as noted in the acknowledgements KEY DRIVERS DIFFICULT CHALLENGES AND FUTURE OPPORTUNITIES Starting with the 2005 edition of the ITRS Test Chapter