I NTERNATIONAL T ECHNOLOGY R OADMAP FOR S EMICONDUCTORS 2003 EDITION TEST AND TEST EQUIPMENT THE ITRS IS DEVISED AND INTENDED FOR TECHNOLOGY ASSESSMENT ONLY AND IS WITHOUT REGARD TO ANY COMMERCIAL CONSIDERATIONS PERTAINING TO INDIVIDUAL PRODUCTS OR EQUIPMENT THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS 2003 TABLE OF CONTENTS Scope 1 Difficult Challenges 1 High Speed Differential Links 2 High Integration Designs 2 Multi die Packaging 3 Known Good Die 3 Reliability Screens 3 Potential Yield Losses 3 Manufacturing Test Cost 4 Reducing Cost Of Testing 6 Reducing Base Cost 6 Reducing Channel Cost 7 Example Product Segments 7 Important Areas Of Concern 9 Test and Yield Learning 9 Physical Failure Analysis 9 Software Based Diagnosis and Signature Analysis 10 Defects and Failure Mechanisms 11 Automated Test Program Generation 11 Modeling and Simulation 12 Test Technology Requirements 15 System on Chip 15 Gigahertz High Frequency Differential Link 18 Important Areas Of Concern 18 High performance ASIC Test Requirements 21 High performance Microprocessor Test Requirements 23 Low end Microcontroller Test Requirements 25 Mixed signal Testing 27 Important Areas Of Concern 27 Equipment for Testing Devices Designed with DFT 30 Semiconductor Memories Test Requirements 32 Commodity Dram Testing 32 Commodity Flash Testing 33 Embedded Dram and Flash Testing 35 THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS 2003 Reliability Technology Requirements 36 Burn In Requirements 37 IDDQ Testing 41 Test Handler and Prober Technology Requirements 42 Device Interface Technology Requirements 50 Probe Cards 50 Trends Affecting Probe Card Technologies 51 Probe Card Technology Requirements 51 Potential Solutions 59 Cross cut Issues 59 Modeling and Simulation 59 LIST OF FIGURES Figure 21 Test and Test Equipment Potential Solutions 59 LIST OF TABLES Table 21 Table 22a Table 22b Table 23a Table 23b Table 24a Table 24b Table 25a Table 25b Table 26a Table 26b Table 27a Table 27b Table 28a Table 28b Table 29a Table 29b Table 30 Table 31a Table 31b Test Equipment Cost Trend per Product Segment 7 Multi site Wafer Test Package Test for Product Segments Near term 8 Multi site Wafer Test Package Test for Product Segments Long term 8 Test and Test Equipment Difficult Challenges Near term 13 Test and Test Equipment Difficult Challenges Long term 14 System on Chip Test Requirements Near term 16 System on Chip Test Requirements Long term 17 Gigahertz High Frequency Differential Link Test Requirements Near Term 20 Gigahertz High Frequency Differential Link Test Requirements Long Term 21 High performance ASIC Test Requirements Near term 22 High performance ASIC Test Requirements Long term 22 High Performance Microprocessor Test Requirements Near term 24 High Performance Microprocessor Test Requirements Long term 25 Low end Microcontroller Test Requirements Near term 26 Low end Microcontroller Test Requirements Long term 26 Mixed signal Test Requirements Near term 28 Mixed signal Test Requirements Long term 29 DFT BIST Device Test Requirements Near term 31 Commodity DRAM Test Requirements Near term 32 Commodity DRAM Test Requirements Long term 33 THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS 2003 Table 32a Table 32b Table 33a Table 33b Table 34a Table 34b Table 35 Table 36a Table 36b Table 37a Table 37b Table 38a Table 38b Table 39a Table 39b Table 40 Table 41 Table 42 Table 43 Table 44 Table 45a Table 45b Commodity Flash Memory Test Requirements Near term 34 Commodity Flash Memory Test Requirements Long term 34 Embedded Memory DRAM and Flash Test Requirements Near term 35 Embedded Memory DRAM and Flash Test Requirements Long term 36 Burn in Requirements Near term 39 Burn in Requirements Long term 40 Projected Performance oriented IC IDDQ Values 41 Handler Memory Pick and Place Requirements Near term 42 Handler Memory Pick and Place Requirements Long term 43 Handler Logic Pick and Place Requirements Near term 44 Handler Logic Pick and Place Requirements Long term 45 Handler Network and Communications Pick and Place Requirements Near term 46 Handler Network and Communications Pick and Place Requirements Long term 47 Prober Logic MPU Pick and Place Requirements Near term 48 Prober Logic MPU Pick and Place Requirements Long term 49 Memory Test Handler Difficult Challenges 50 Logic Test Handler Difficult Challenges 50 Network and Communications Test Handler Difficult Challenges 50 Logic Test Prober Difficult Challenges 50 Probe Card Difficult Challenges Near term 51 Wafer Probe Technology Requirements Near term 54 Wafer Probe Technology Requirements Long term 57 THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS 2003 Test and Test Equipment 1 TEST AND TEST EQUIPMENT SCOPE The 2003 Test Roadmap has continued to expand scope from the 2001 edition Increased focus has been placed on emerging difficult challenges to improve coverage of these topics and this content of the test roadmap is expected to grow and mature with future roadmap revisions This revision cycle finds the test equipment industry at the beginning of a significant shift from traditional test architectures to universal slot architectures with high levels of test instrument encapsulation and modularity This shift has been enabled by the continued evolution of technology and increased integration level of design components In many cases a single Field Programmable Gate Array FPGA or Application Specific Integrated Circuit ASIC is able to take the place of entire subsystems of electronics in older tester designs Encapsulation and modularity has led to the concept of Open Architecture the ability to mix and match test instruments from multiple suppliers into a single tester hardware and software environment This concept raises significant business model challenges to the test equipment industry an industry that is today based on full vertical integration and proprietary platforms However there are several potential advantages of an open architecture approach Focus research and development investment both dollars and effort on the test instrument itself rather than test infrastructure Differentiation based on test capability rather than platform Suppliers focus on development of solutions within their particular core competency reducing cost and speeding time to market Reduces the investment in re engineering infrastructural elements Eliminates the need for each supplier to be everything to everyone a very difficult position to achieve In the