THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2003 INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS 2003 EDITION TEST AND TEST EQUIPMENT THE ITRS IS DEVISED AND INTENDED FOR TECHNOLOGY ASSESSMENT ONLY AND IS WITHOUT REGARD TO ANY COMMERCIAL CONSIDERATIONS PERTAINING TO INDIVIDUAL PRODUCTS OR EQUIPMENT.THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2003 TABLE OF CONTENTS Scope................................................................................................................................... 1 Difficult Challenges............................................................................................................... 1 High Speed Differential Links.........................................................................................................2 High Integration Designs ...............................................................................................................2 Multi-die Packaging......................................................................................................................................3 Known Good Die ..........................................................................................................................................3 Reliability Screens.........................................................................................................................3 Potential Yield Losses ...................................................................................................................3 Manufacturing Test Cost................................................................................................................4 Reducing Cost Of Testing ............................................................................................................................6 Reducing Base Cost.....................................................................................................................................6 Reducing Channel Cost ...............................................................................................................................7 Example Product Segments.........................................................................................................................7 Important Areas Of Concern ........................................................................................................................9 Test and Yield Learning.................................................................................................................9 Physical Failure Analysis..............................................................................................................................9 Software-Based Diagnosis and Signature Analysis...................................................................................10 Defects and Failure Mechanisms...............................................................................................................11 Automated Test Program Generation ..........................................................................................11 Modeling and Simulation .............................................................................................................12 Test Technology Requirements.......................................................................................... 15 System on Chip...........................................................................................................................15 Gigahertz High Frequency Differential Link..................................................................................18 Important Areas Of Concern ......................................................................................................................18 High-performance ASIC Test Requirements ...............................................................................21 High-performance Microprocessor Test Requirements................................................................23 Low-end Microcontroller Test Requirements................................................................................25 Mixed-signal Testing....................................................................................................................27 Important Areas Of Concern ......................................................................................................................27 Equipment for Testing Devices Designed with DFT.....................................................................30 Semiconductor Memories Test Requirements .............................................................................32 Commodity Dram Testing...........................................................................................................................32 Commodity Flash Testing...........................................................................................................................33 Embedded Dram and Flash Testing...........................................................................................................35THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2003 Reliability Technology Requirements..................................................................................36 Burn-In Requirements..................................................................................................................37 IDDQ Testing...............................................................................................................................41 Test Handler and Prober Technology Requirements..........................................................42 Device Interface Technology Requirements .......................................................................50 Probe Cards ................................................................................................................................50 Trends Affecting Probe Card Technologies .............................................................................................. 51 Probe Card Technology Requirements..................................................................................................... 51 Potential Solutions ..............................................................................................................59 Cross-cut Issues.................................................................................................................59