1ECE 269: VLSI System Testing Spring 2009 Krish Chakrabarty Term Project Topics January 20, 2009 Outline This handout describes the term project requirements and deadlines, and lists some possible topics for projects. Proposals for projects on other topics of your choice are welcome. Project Selection Select a project from the list below, or propose a new project. You must complete a project in order to receive a grade in this course. Projects may be proposed by individual students or by a team of two students. (The latter is recommended only for large programming or design projects.) You will find relevant reference material in the text and in various VLSI CAD journals and conference proceedings (in the library or on the web⎯IEEE Explore, ACM Digital Library, Google Scholar, etc.). Some reading and thinking is necessary in order to select and assess a project; the time spent doing this now will pay off later. Proposal You are required to submit a short proposal (two typed pages maximum, excluding appendices), no later than January 27. Projects will be assigned by the instructor based on the quality of the proposals. The proposal should contain the following: • Titles, author name(s) and e-mail address(es) • Project outline: objectives, work plan, expected results, and other pertinent data • Time schedule listing dates of major “milestones” • Work division (two-person projects only) • References (only those used in preparing the proposal) Every effort will be made to give students their first choice. However, you may be asked to submit a revised or new proposal. You should therefore have a back-up project in mind. Progress reports A brief one-page written progress report will be due on February 26. This report should summarize how the project is progressing, describe any unexpected difficulties encountered, and outline any major changes in the project plan. Oral presentation The class hour on April 14 has been reserved for oral presentations, and where appropriate, for demonstrations. An additional evening slot may also be reserved. Presentations will be for 15-20 minutes per project. In addition, project overview presentations may be scheduled for February.2Written report You are required to submit a formal term report due by April 14. This report will be a major factor in determining project grades. The term reports should be of professional quality and be in the format of a technical report or journal paper. The experimental projects may have shorter reports, with detailed material such as program listings, sample runs, etc. placed in appendices. All reports must contain the following: • Title page • Abstract (summary of report) • Introduction (problem definition, background material, prior work, goals and methods) • Project results in one or more sections • Conclusions (evaluation of results, suggestions for improvement or future work) • References • Appendices (if appropriate) Suggested project topics 1. [Wafer-Level Test During Burn-In] Wafer-level test during burn-in (WLTBI) is a promising technique to reduce test and burn-in costs in semiconductor manufacturing. However, scan-based testing leads to significant power variations in a die during test-pattern application. This variation adversely affects the accuracy of predictions of junction temperatures and the time required for burn-in. The problem of controlling the variation in power consumption during WLTBI has recently been addressed in [1, 2]. In [2], a test pattern reordering technique was proposed to control the variation in test power during WLTBI. There are several other methods that can be adopted to solve the problem of controlling test power variation for WLTBI. One potential approach that can be employed is reordering of the scan flip-flops in scan chains such that the power variation during WLTBI can be minimized further. The problem can be briefly stated as follows: for a given a circuit (with full scan design) and a set of test vectors, reorder the flip-flops in the scan chain, such that variation in power consumption is reduced. The power consumption during test can be estimated by computing the number of flop transitions occurring during test in the scan chains. The goal of the project is to develop a solution for the above mentioned problem, or explore alternate solutions to address the test power/thermal related problems during WLTBI. Expected project deliverables: 1) Clearly formulate the problem with a set of knows and unknowns. Determine a solution approach to solve the problem; analyze the complexity of the solution to obtain optimal solutions. 2) If the problem is computationally complex, develop a heuristic methodology to solve the problem with reasonable loss of accuracy in the solution. 3) Experiments are to be reported for the ISCAS’89 benchmark circuits by comparing the results of your approach with appropriate baseline scenarios. References: • S. Bahukudumbi and K. Chakrabarty, “Test-Pattern Ordering for Wafer-Level Test-During-Burn-In”, IEEE VLSI Test Symposium, pp. 193-198, 2008.3• S. Bahukudumbi and K. Chakrabarty, "Power management for wafer-level test during burn-in", IEEE Asian Test Symposium, pp. 231-236, 2008. 2. [Testing for IR-Drop and Power-Supply Noise] As technology shrinks to less than 65 nm and functional density continues to rise, IR-drop and power supply noise (PSN) are becoming significant in the design and test of integrated circuits. Timing closure and functional verification cannot be considered to be complete until pre- and post-layout IR-drop, ground bounce, and PSN effect have been estimated and the appropriate margins applied. These effects have complex interdependencies and conventional design tools do not have the capability to consider all of these effects and their interrelationships concurrently. On-chip monitoring, careful power-ground network planning, worst-case IR-drop prediction, pattern generation for maximum supply noise, path delay analysis considering IR-drop and PSN are among the strategies and methods that should be used. Survey the state-of-the-art in this emerging (and exciting) research area and identify research directions. References: • N. Ahmed, M. Tehranipoor and V. Jayaram, “Supply Voltage Noise Aware ATPG for Transition Delay Faults,” IEEE VLSI Test Symposium (VTS'07), 2007. • N. Ahmed, M. Tehranipoor and V. Jayaram, “A Novel Framework for