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Duke ECE 269 - Sequential Circuit ATPG

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1ECE 269Krish Chakrabarty1ECE 269VLSI System TestingKrish ChakrabartySequential Circuit ATPGECE 269Krish Chakrabarty2Sequential Circuits• A sequential circuit has memory in addition to combinational logic.• Test for a fault in a sequential circuit is a sequence of vectors, which• Initializes the circuit to a known state• Activates the fault, and• Propagates the fault effect to a primary output• Methods of sequential circuit ATPG• Time-frame expansion methods• Simulation-based methods2ECE 269Krish Chakrabarty3Testing Sequential Circuits• Difficult problem-internal states cannot be directly controlled and observed• Long test sequences are necessaryCombinationallogicRegistersPrimaryinputsPrimaryoutputs(controllable)(observable)State outputs(not observable)State inputs(not controllable)ECE 269Krish Chakrabarty4TaxonomySequential ATPGSynchronous AsynchronousState-table gate-level RTL-level + simulation- topologicalBased gate-level based analysis basedTopological Simulation- Hybridanalysis based based Known Unknowninitial state initial state3ECE 269Krish Chakrabarty5Fault Classification• Modes of operation– Synchronization mode: operation starts with specified synchronizing sequence– Free mode: no synchronization is done• Test generation approaches– Single observation time (SOT)– Multiple observation time (MOT)ECE 269Krish Chakrabarty6Single Observation Time• Definition: A fault f is detectable if there exists an input sequence I such that for every pair of initial states S and Sfof the fault-free and faulty circuits, respectively, the response z(I,S) of the fault-free circuit is different from the response z(I,Sf) of the faulty circuit at a specifiedtime unit j.• Motivation: Observe test responses at certain time units only, simpler testing strategy4ECE 269Krish Chakrabarty7Multiple Observation Time• Definition: A fault f is detectable if there exists an input sequence I such that for every pair of initial states S and Sfof the fault-free and faulty circuits, respectively, the response z(I,S) of the fault-free circuit is different from the response z(I,Sf) of the faulty circuit at sometime unit j.• Every fault detected under SOT is also detectable under MOT, reverse not true• MOT detects more faults (shorter test lengths) but difficult to implementECE 269Krish Chakrabarty8SOT vs MOTFF01MUXaczstuck-at-0Initial state unknownSOT approach:no test exists, faultundetectableMOT approach:• Fault detected by inputsequence (a,c) = {(1,1),(0,1)}Fault-free output sequence: {1,0}Faulty output (initial state = 0): {0,0}Faulty output (initial state = 1): {1,1}Fault detected (need to observe for both time steps)!5ECE 269Krish Chakrabarty9Iterative Logic Array (ILA) Modelx1x2. . .xnx1x2. . .xnTimeframe 1Timeframe 2. . .z1z2zt. . .z1z2zty1y2ymY1Y2Ymy1y2ymSSL fault must be treated as a “multiple fault”, present in every time framex1x2. . .xnTimeframe N. . .z1z2zty1y2ym...ECE 269Krish Chakrabarty10Extended D-Algorithmx1zyx2• Start with time frame 0• Propagate error to primary output by forward time processing• Justify state by reverse time processingx1zyx2x1zyx2Time frame 0 Time frame 1Time frame -1101s-a-0s-a-0s-a-010DDD010Test sequence: (x1,x2) = {(X,0),(1,1),(X,1)}6ECE 269Krish Chakrabarty119-Valued Logicx1zyx2Time frame -11s-a-00x1yx2Time frame 00s-a-01z110DD01Contradictionx1zyx2Time frame -1x1yx2Time frame 0zs-a-05-valuedlogic1/00/10/X1/X0/X1/0s-a-00/X1/11/X1/X9-valuedlogic1/X0/XTestfoundECE 269Krish Chakrabarty12State Justification Decision TreeStartGoal: Make all state variables XUntriedalternativesAlready visitedStopAn example withtwo flip-flops(y1,y2)(0,1)(X,1)(0,1)(1,1)(X,X)SUCCESSStopUntriedalternatives• Keep track of statesalready visited7ECE 269Krish Chakrabarty13Simulation-Based ATPG: Motivation• Difficulties with time-frame method:• Long initialization sequence• Impossible initialization with three-valued logic (Section 5.3.4)• Circuit modeling limitations• Timing problems – tests can cause races/hazards• High complexity• Inadequacy for asynchronous circuits• Advantages of simulation-based methods• Advanced fault simulation technology• Accurate simulation model exists for verification• Variety of tests – functional, heuristic, random• Used since early 1960sECE 269Krish Chakrabarty14Simulation-Based ATPG• Genetic algorithms• Advantages: less CPU time than ILA model methods• Disadvantages: cannot identify undetectable faults, longer test sequences– Biologically-inspired– Initial population (test sequences), perform selection, mutation, and crossover operations– Fitness function used• Challenge: How to determine fitness function?8ECE 269Krish Chakrabarty15Using Fault SimulatorYesFaultsimulatorVector source:Functional (test-bench),Heuristic (walking 1, etc.),Weighted random,randomFaultlistTestvectorsNew faultsdetected?Stoppingcriteria(faultcoverage, CPUtime limit, etc.)satisfied?StopUpdatefaultlistAppendvectorsRestorecircuitstateGeneratenew trialvectorsYes NoNoTrial


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