ECE 538 VLSI System Testing Krish Chakrabarty Sequential Circuit ATPG ECE 538 Krish Chakrabarty 1 Sequential Circuits A sequential circuit has memory in addition to combinational logic Test for a fault in a sequential circuit is a sequence of vectors which Initializes the circuit to a known state Activates the fault and Propagates the fault effect to a primary output Methods of sequential circuit ATPG Time frame expansion methods Simulation based methods ECE 538 Krish Chakrabarty 2 1 Testing Sequential Circuits Difficult problem internal states cannot be directly controlled and observed Long test sequences are necessary Primary inputs controllable Primary outputs observable Combinational logic State inputs not controllable State outputs not observable Registers Krish Chakrabarty ECE 538 3 Taxonomy Sequential ATPG Synchronous State table gate level RTL level Based gate level Topological analysis based Asynchronous simulationbased topological analysis based Simulation Hybrid based Known Unknown initial state initial state ECE 538 Krish Chakrabarty 4 2 Fault Classification Modes of operation Synchronization mode operation starts with specified synchronizing sequence Free mode no synchronization is done Test generation approaches Single observation time SOT Multiple observation time MOT ECE 538 Krish Chakrabarty 5 Single Observation Time Definition A fault f is detectable if there exists an input sequence I such that for every pair of initial states S and Sf of the fault free and faulty circuits respectively the response z I S of the fault free circuit is different from the response z I Sf of the faulty circuit at a specified time unit j Motivation Observe test responses at certain time units only simpler testing strategy ECE 538 Krish Chakrabarty 6 3 Multiple Observation Time Definition A fault f is detectable if there exists an input sequence I such that for every pair of initial states S and Sf of the fault free and faulty circuits respectively the response z I S of the fault free circuit is different from the response z I Sf of the faulty circuit at some time unit j Every fault detected under SOT is also detectable under MOT reverse not true MOT detects more faults shorter test lengths but difficult to implement Krish Chakrabarty ECE 538 7 SOT vs MOT Initial state unknown 0 MUX a ECE 538 z 1 c SOT approach no test exists fault undetectable FF stuck at 0 MOT approach Fault detected by input sequence a c 1 1 0 1 Fault free output sequence 1 0 Faulty output initial state 0 0 0 Faulty output initial state 1 1 1 Fault detected need to observe for both time steps Krish Chakrabarty 8 4 Iterative Logic Array ILA Model x1 x2 xn y1 Y1 y1 Time Y2 y2 Time frame 1 frame 2 Ym ym y2 ym z1 z2 zt x1 x2 xn x1 x2 xn y1 y2 Time frame N ym z1 z2 zt z1 z2 zt SSL fault must be treated as a multiple fault present in every time frame Krish Chakrabarty ECE 538 9 Extended D Algorithm Start with time frame 0 Propagate error to primary output by forward time processing Justify state by reverse time processing s a 0 s a 0 1 1 x1 x2 0 y x1 s a 0 D 1 x2 x1 x D 1 2 y 0 z Time frame 1 0 z Time frame 0 0 y z D Time frame 1 Test sequence x1 x2 X 0 1 1 X 1 ECE 538 Krish Chakrabarty 10 5 9 Valued Logic s a 0 s a 0 Contradiction x1 x1 1 0 z 1 0 x2 x2 y 1 Time frame 1 x1 1 X 0 x1 z 9 valued 1 0 s a 0 0 1 logic 0 X 0 X 1 X D Time frame 0 y Test found s a 0 1 z 0 1 5 valued logic D z 1 1 0 X x2 1 X x2 y 1 X Time frame 1 y 1 0 0 X Time frame 0 Krish Chakrabarty ECE 538 11 State Justification Decision Tree An example with two flip flops Start Goal Make all state variables X 0 1 y1 y2 Untried alternatives X 1 Already visited Stop 0 1 SUCCESS Stop X X ECE 538 Keep track of states already visited 1 1 Untried alternatives Krish Chakrabarty 12 6 Simulation Based ATPG Motivation Difficulties with time frame method Long initialization sequence Impossible initialization with three valued logic Section 5 3 4 Circuit modeling limitations Timing problems tests can cause races hazards High complexity Inadequacy for asynchronous circuits Advantages of simulation based methods ECE 538 Advanced fault simulation technology Accurate simulation model exists for verification Variety of tests functional heuristic random Used since early 1960s Krish Chakrabarty 13 Simulation Based ATPG Genetic algorithms Advantages less CPU time than ILA model methods Disadvantages cannot identify undetectable faults longer test sequences Biologically inspired Initial population test sequences perform selection mutation and crossover operations Fitness function used Challenge How to determine fitness function ECE 538 Krish Chakrabarty 14 7 Using Fault Simulator Vector source Functional test bench Heuristic walking 1 etc Weighted random random Generate new trial vectors No Trial vectors Stopping Yes criteria fault coverage CPU time limit etc satisfied Stop ECE 538 No Fault simulator Fault list Restore circuit state New faults detected Krish Chakrabarty Yes Update fault list Append vectors Test vectors 15 8
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