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Duke ECE 269 - Sequential Circuit ATPG

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1 ECE 538 Krish Chakrabarty 1 ECE 538!VLSI System Testing!Krish Chakrabarty! Sequential Circuit ATPG!ECE 538 Krish Chakrabarty 2 Sequential Circuits • A sequential circuit has memory in addition to combinational logic. • Test for a fault in a sequential circuit is a sequence of vectors, which • Initializes the circuit to a known state • Activates the fault, and • Propagates the fault effect to a primary output • Methods of sequential circuit ATPG • Time-frame expansion methods • Simulation-based methods2 ECE 538 Krish Chakrabarty 3 Testing Sequential Circuits!• Difficult problem-internal states cannot be directly controlled and observed!• Long test sequences are necessary!Combinational!logic!Registers!Primary!inputs!Primary!outputs!(controllable)!(observable)!State outputs!(not observable)!State inputs!(not controllable)!ECE 538 Krish Chakrabarty 4 Taxonomy!Sequential ATPG!Synchronous ! !!Asynchronous!State-table gate-level RTL-level + simulation- topological!Based gate-level based analysis based!Topological Simulation- Hybrid!analysis based based !Known Unknown!initial state initial state!3 ECE 538 Krish Chakrabarty 5 Fault Classification!• Modes of operation!– Synchronization mode: operation starts with specified synchronizing sequence!– Free mode: no synchronization is done!• Test generation approaches!– Single observation time (SOT)!– Multiple observation time (MOT)!ECE 538 Krish Chakrabarty 6 Single Observation Time!• Definition: A fault f is detectable if there exists an input sequence I such that for every pair of initial states S and Sf of the fault-free and faulty circuits, respectively, the response z(I,S) of the fault-free circuit is different from the response z(I,Sf) of the faulty circuit at a specified time unit j.!• Motivation: Observe test responses at certain time units only, simpler testing strategy!4 ECE 538 Krish Chakrabarty 7 Multiple Observation Time!• Definition: A fault f is detectable if there exists an input sequence I such that for every pair of initial states S and Sf of the fault-free and faulty circuits, respectively, the response z(I,S) of the fault-free circuit is different from the response z(I,Sf) of the faulty circuit at some time unit j.!• Every fault detected under SOT is also detectable under MOT, reverse not true!• MOT detects more faults (shorter test lengths) but difficult to implement!ECE 538 Krish Chakrabarty 8 SOT vs MOT!FF!0!1!MUX!a!c!z!stuck-at-0!Initial state unknown!SOT approach:! no test exists, fault! undetectable!MOT approach:!• Fault detected by input! sequence (a,c) = {(1,1),(0,1)}!Fault-free output sequence: {1,0}!Faulty output (initial state = 0): {0,0}!Faulty output (initial state = 1): {1,1}!Fault detected (need to observe for both time steps)!!5 ECE 538 Krish Chakrabarty 9 Iterative Logic Array (ILA) Model!x1!x2!. . .!xn!x1!x2!. . .!xn!Time!frame 1!Time!frame 2!. . .!z1!z2! zt!. . .!z1!z2! zt!y1!y2!ym!Y1!Y2!Ym!y1!y2!ym!SSL fault must be treated as a “multiple fault”, present in every time frame!x1!x2!. . .!xn!Time!frame N!. . .!z1!z2! zt!y1!y2!ym!.!.!.!ECE 538 Krish Chakrabarty 10 Extended D-Algorithm!x1!z!y!x2!• Start with time frame 0 • Propagate error to primary output by forward time processing • Justify state by reverse time processing x1!z!y!x2!x1!z!y!x2!Time frame 0 Time frame 1 Time frame -1 1!0!1!s-a-0!s-a-0!s-a-0!1!0!D!D!D!0!1!0!Test sequence: (x1,x2) = {(X,0),(1,1),(X,1)}6 ECE 538 Krish Chakrabarty 11 9-Valued Logic!x1!z!y!x2!Time frame -1 1!s-a-0!0!x1!y!x2!Time frame 0 0!s-a-0!1!z!1!1!0!D!D!0!1!Contradiction x1!z!y!x2!Time frame -1 x1!y!x2!Time frame 0 z!s-a-0!5-valued logic 1/0!0/1!0/X!1/X!0/X!1/0!s-a-0!0/X!1/1!1/X!1/X!9-valued logic 1/X!0/X!Test found ECE 538 Krish Chakrabarty 12 State Justification Decision Tree Start Goal: Make all state variables X Untried alternatives Already visited Stop An example with two flip-flops (y1,y2) (0,1) (X,1) (0,1) (1,1) (X,X) SUCCESS Stop Untried alternatives • Keep track of states already visited7 ECE 538 Krish Chakrabarty 13 Simulation-Based ATPG: Motivation • Difficulties with time-frame method: • Long initialization sequence • Impossible initialization with three-valued logic (Section 5.3.4) • Circuit modeling limitations • Timing problems – tests can cause races/hazards • High complexity • Inadequacy for asynchronous circuits • Advantages of simulation-based methods • Advanced fault simulation technology • Accurate simulation model exists for verification • Variety of tests – functional, heuristic, random • Used since early 1960s ECE 538 Krish Chakrabarty 14 Simulation-Based ATPG • Genetic algorithms • Advantages: less CPU time than ILA model methods • Disadvantages: cannot identify undetectable faults, longer test sequences – Biologically-inspired – Initial population (test sequences), perform selection, mutation, and crossover operations – Fitness function used • Challenge: How to determine fitness function?8 ECE 538 Krish Chakrabarty 15 Using Fault Simulator Yes Fault simulator Vector source: Functional (test-bench), Heuristic (walking 1, etc.), Weighted random, random Fault list Test vectors New faults detected? Stopping criteria (fault coverage, CPU time limit, etc.) satisfied? Stop Update fault list Append vectors Restore circuit state Generate new trial vectors Yes No No Trial


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