1ECE 269Krish Chakrabarty1ECE 269VLSI System TestingKrish ChakrabartyLecture 7:Fault SimulationECE 269Krish Chakrabarty2Fault Simulation• Problem and motivation• Fault simulation algorithms•Serial•Parallel• Deductive• Concurrent• Random Fault Sampling•Summary2ECE 269Krish Chakrabarty3Problem and Motivation• Fault simulation Problem: Given A circuit A sequence of test vectors A fault model– Determine Fault coverage - fraction (or percentage) of modeled faults detected by test vectors Set of undetected faults• Motivation Determine test quality and in turn product quality Find undetected fault targets to improve testsECE 269Krish Chakrabarty4Motivation• Simulate a circuit in the presence of faults• Given test set T, determine the fault coverage of T (test grading)– Fraction of faults (percentage) detected by T• How is fault coverage related to defect coverageand yield?DL = 1 − Y1−dDL (defect level): Probability of shipping a defective chipY: yield, d: fault (defect) coveragee.g. if Y = 0.5, 99% fault coverage needed to achieve 0.01 defect level95% fault coverage implies 0.035 defect level3ECE 269Krish Chakrabarty5Applications• Evaluate effects (criticality) of faults• Evaluate fault coverage of given test set• Generate fault dictionaries (for diagnosis)• Aid in test pattern generation– Fault dropping– Test set compaction– Simulation-based and random test generationECE 269Krish Chakrabarty6Fault simulator in a VLSI Design ProcessVerified designnetlistVerificationinput stimuliFault simulator Test vectorsModeledfault listTestgeneratorTestcompactorFaultcoverage?Remove tested faultsDeletevectorsAdd vectorsLowAdequateStop4ECE 269Krish Chakrabarty7Use in Test GenerationGenerate initial TSufficientfaultcoverage?Evaluate TModify TNoYesDoneSelecttarget faultGenerate testfor targetFault simulateDiscarddetected faultsDoneNo morefaultsECE 269Krish Chakrabarty8Fault Simulation Scenario• Circuit model: mixed-level• Mostly logic with some switch-level for high-impedance (Z) and bidirectional signals• High-level models (memory, etc.) with pin faults• Signal states: logic• Two (0, 1) or three (0, 1, X) states for purely Boolean logic circuits• Four states (0, 1, X, Z) for sequential MOS circuits• Timing:• Zero-delay for combinational and synchronous circuits• Mostly unit-delay for circuits with feedback5ECE 269Krish Chakrabarty9Fault Simulation Scenario (continued)•Faults:• Mostly single stuck-at faults• Sometimes stuck-open, transition, and path-delay faults; analog circuit fault simulators are not yet in common use• Equivalence fault collapsing of single stuck-at faults• Fault-dropping -- a fault once detected is dropped from consideration as more vectors are simulated; fault-dropping may be suppressed for diagnosis• Fault sampling -- a random sample of faults is simulated when the circuit is largeECE 269Krish Chakrabarty10Fault Simulation Algorithms•Serial• Parallel• Deductive• Concurrent6ECE 269Krish Chakrabarty11Serial Algorithm• Algorithm: Simulate fault-free circuit and save responses. Repeat following steps for each fault in the fault list:• Modify netlist by injecting one fault• Simulate modified netlist, vector by vector, comparing responses with saved responses• If response differs, report fault detection and suspend simulation of remaining vectors• Advantages:• Easy to implement; needs only a true-value simulator, less memory• Most faults, including analog faults, can be simulatedECE 269Krish Chakrabarty12Serial Algorithm (Cont.)• Disadvantage: Much repeated computation; CPU time prohibitive for VLSI circuits• Alternative: Simulate many faults togetherTest vectorsFault-free circuit Circuit with fault f1Circuit with fault f2Circuit with fault fnComparator f1 detected?Comparator f2 detected?Comparator fn detected?7ECE 269Krish Chakrabarty13Parallel Fault Simulation• Compiled-code method; best with two-states (0,1)• Exploits inherent bit-parallelism of logic operations on computer words• Storage: one word per line for two-state simulation• Multi-pass simulation: Each pass simulates w-1 new faults, where w is the machine word length• Speed up over serial method ~ w-1• Not suitable for circuits with timing-critical and non-Boolean logicECE 269Krish Chakrabarty14Parallel Fault Simulation Examplea b c d e f g 1 1 11 1 11 0 11 0 10 0 01 0 1s-a-1s-a-00 0 1c s-a-0 detectedBit 0: fault-free circuitBit 1: circuit with c s-a-0Bit 2: circuit with f s-a-18ECE 269Krish Chakrabarty15Limitations of Parallel Fault Simulation • Useful for two (1,0) or three (0,1,X) logic values, not suitable for multiple logic values, e.g. (0,1,U,R,F,…)– Multiple logic values can be handled but operations are complex• Wasted computations– Fault dropping not carried out effectively– Not possible to discard faults that are in the same wordECE 269Krish Chakrabarty16Deductive Fault Simulation• One-pass simulation• Each line k contains a list Lkof faults detectable on k • Following true-value simulation of each vector, fault lists of all gate output lines are updated using set-theoretic rules, signal values, and gate input fault lists• PO fault lists provide detection data• Limitations:• Set-theoretic rules difficult to derive for non-Boolean gates• Gate delays are difficult to use9ECE 269Krish Chakrabarty17Deductive Fault SimulationExamplea b c d e f g 11101{a0}{b0, c0}{b0}{b0, d0}Le= LaU LcU {e0}= {a0, b0, c0, e0}Lg= (LeLf ) U {g0}= {a0, c0, e0, g0}U{b0, d0, f1}Notation: Lkis fault list for line kknis s-a-n fault on line k Faults detected bythe input vector1ECE 269Krish Chakrabarty18Fault List PropagationConsider an AND gate Z = A.B, and let A = B = 1Then LZ= LA∪ LB∪ {Z s-a-0}Let A = 0 and B = 1Then LZ= {LA∩ LB} ∪ {Z s-a-1} = (LA− LB) ∪ {Z s-a-1}In general, let I be the set of inputs of gate Z with controlling value cand inversion i. Let C be the set of inputs with value c.if C = ∅ then LZ= {∪ Lj} ∪ {Z s-a-(c ⊕ i)}else LZ= {∩ Lj} − {∪ Lj} ∪{Z s-a-(c ⊕ i)}j ∈ Ij ∈ Cj ∈ I − C• If no input has value c then fault effect on an input propagates to output• If some inputs have value c, only faults that affect inputs with c (not c)propagates to output10ECE 269Krish Chakrabarty19Deductive Simulation ExamplebacdefghijkmFault set (after fault collapsing): {a/0, a/1, b/1, c/0, c/1, d/1, e/0, g/0, h/0,