Duke ECE 269 - Memory Testing (8 pages)

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Memory Testing



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Memory Testing

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Pages:
8
School:
Duke University
Course:
Ece 269 - VLSI System Testing

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ECE 269 VLSI System Testing Krish Chakrabarty Memory Testing ECE 269 Krish Chakrabarty 1 Density Density Trends Trends 1970 DRAM Invention Intel 1024 bits 1993 1st 256 MBit DRAM papers 1997 1st 256 MBit DRAM samples 1 bit 120 X 10 6 bit ECE 269 Krish Chakrabarty 2 1 Memory Memory Cells Cells Per Per Chip Chip Krish Chakrabarty ECE 269 3 Test Test Time Time in in Seconds Seconds Memory Memory Size Size nn Bits Bits Size n Number of Test Algorithm Operations n 0 06 1 Mb 0 25 4 Mb 16 Mb 1 01 64 Mb 4 03 256 Mb 16 11 64 43 1 Gb 128 9 2 Gb ECE 269 n log2n n3 2 n2 1 26 5 54 24 16 104 7 451 0 1932 8 3994 4 64 5 515 4 1 2 hr 9 2 hr 73 3 hr 586 4 hr 1658 6 hr 18 3 hr 293 2 hr 4691 3 hr 75060 0 hr 1200959 9 hr 19215358 4 hr 76861433 7 hr Krish Chakrabarty 4 2 Outline RAM structure Fault models Opens shorts and stuck at faults Address decoder faults inaccessible cells or multiple cell accesses Coupling and pattern sensitive faults interactions between neighboring cells Standard RAM tests March tests Finite sequence of March elementts i e finite sequence of operations applied to every cell before proceeding to next cell Checkerboard Walking 1s and 0s Galloping pattern of 1s and 0s GALPAT Reference A J Van de Goor Testing Semiconductor Memories Theory and Practice John Wiley 1991 Krish Chakrabarty ECE 269 5 RAM Structure Address buffer Row decoders Address Storage array Sense amplifier Refresh Control DRAM Column decoder Data buffer Control Data In Out ECE 269 Krish Chakrabarty 6 3 Fault Models Fault models are technology dependent Stuck at fault SAF A cell is always in state 0 s a 0 or state 1 s a 1 Transition fault TF Special case of SAF Cell unable to make 0 1 transition when 1 is written to it up transition fault symbol 0 Cell unable to make 1 0 transition when 0 is written to it down transition fault symbol 1 Krish Chakrabarty ECE 269 7 Fault Models w0 w1 w1 S1 w0 State diagram of fault free cell S0 w0 w0 w1 S0 S1 w1 State diagram of s a 1 cell State diagram of s a 0 cell w1



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