Tutorial2940740-7475/06/$20.00 © 2006 IEEE Copublished by the IEEE CS and the IEEE CASS IEEE Design & Test of ComputersTHE AMOUNT OF DATA required to test ICs is growingrapidly in each new generation of technology. Increasingintegration density results in larger designs with more scancells and more faults. Moreover, achieving high test qual-ity in ever smaller geometries requires more test patternstargeting delay faults and other fault models beyond stuck-at faults. Conventional external testing involves storing alltest vectors and test response on an external tester—thatis, ATE. But these testers have limited speed, memory, andI/O channels. The test data bandwidth between the testerand the chip is relatively small; in fact, it is often the bot-tleneck determining how fast you can test the chip. Testingcannot proceed any faster than the amount of timerequired to transfer the test data:Test time ≥ (amount of test data on tester) / (numberof tester channels × tester clock rate)Overcoming limited tester-chipbandwidthThree general approaches help overcome this bottle-neck: stand-alone BIST, hybrid BIST, and test data com-pression.Stand-alone BISTTraditional stand-alone BIST involves using on-chiphardware to perform all test pattern generation and out-put response analysis. Stand-alone BIST eliminates theneed for tester storage. This is very useful for perform-ing self-test in the field when there is no access to atester. However, achieving high fault cov-erage with stand-alone BIST generallyrequires considerable overhead becauseof random-pattern-resistant (RPR) faults,which have low detection probabilities.Detecting such faults requires either testpoints or deterministic-pattern-embed-ding logic. Other issues with BIST includethe need for a BIST-ready design, a way to handle falseand multicycle paths, and the need to keep nondeter-ministic values from corrupting the final signature.Hybrid BISTIf a particular chip design uses BIST only for manufac-turing test, then hybrid BIST can be more cost-effectivethan stand-alone BIST. Hybrid BIST involves storing somedata on the tester to help detect RPR faults. The simplestapproach is to perform ATPG for RPR faults not detectedby pseudorandom BIST to obtain a set of deterministic testpatterns that “top up” the fault coverage to the desiredlevel, and then store those patterns directly on the tester.More efficient hybrid BIST schemes store the deter-ministic top-up patterns on the tester in a compressedform, then use the existing BIST hardware to decompressthese patterns. Some schemes embed deterministic pat-terns by using compressed weight sets or by perturbingthe pseudorandom sequence in some manner.Test data compressionAs Figure 1 illustrates, test data compression involvesadding some additional on-chip hardware before andafter the scan chains. This additional hardware decom-presses the test stimulus coming from the tester; it alsocompacts the response after the scan chains and beforeit goes to the tester. This permits storing the test data in acompressed form on the tester. With test data compres-sion, the tester still applies a precise deterministic(ATPG-generated) test set to the circuit under test (CUT).Survey of Test VectorCompression TechniquesTest data compression consists of test vector compression on the input sideand response compaction on the output side. Test vector compression hasbeen an active area of research, yielding a wide variety of techniques. Thisarticle summarizes and categorizes these techniques, explaining how theyrelate to one another. The goal is to provide a framework for understandingthe theory and research in this area.Nur A. ToubaUniversity of Texas at AustinThis process differs from that of hybrid BIST, whichapplies a large number of patterns, including bothpseudorandom and deterministic data. Although hybridBIST can reduce the amount of test data on the testermore than test data compression can, hybrid BIST gen-erally requires longer test application time because youmust apply more patterns to the CUT than with test datacompression (in essence, hybrid BIST trades off moretest application time for less tester storage). The advan-tage of test data compression is that it generates thecomplete set of patterns applied to the CUT with ATPG,and this set of test patterns is optimizable with respectto the desired fault coverage. Test data compression isalso easier to adopt in industry because it’s compatiblewith the conventional design rules and test generationflows for scan testing.Test data compression provides two benefits. First, itreduces the amount of data stored on the tester, whichcan extend the life of older testers that have limitedmemory. Second—and this is the more important ben-efit, which applies even for testers with plenty of mem-ory—it can reduce the test time for a given test databandwidth. Doing so typically involves having thedecompressor expand the data from n tester channelsto fill greater than n scan chains. Increasing the numberof scan chains shortens each scan chain, in turn reduc-ing the number of clock cycles needed to shift in eachtest vector.Test data compression must compress the test vec-tors losslessly (that is, it must reproduce all the care bitsafter decompression) to preserve fault coverage. Theoutput response, on the other hand, can use lossy com-paction (which does not reproduce all data, losinginformation) with negligible impact on fault coverage.Ideally, the output response could be compacted usingjust a multiple-input signature register (MISR). Howeverany unknown (nondeterministic) values in the outputresponse would corrupt the final signature. Researchershave developed several schemes to address the prob-lem of unknown values in the output response, includ-ing eliminating the source of the unknown values,selectively masking the unknown values in the outputstream, or using an output compaction scheme that cantolerate the unknown values. Output compaction is anentire subject in itself, and I will not discuss it further inthis article.The subject here is test vector compression tech-niques. Test vectors are highly compressible becausetypically only 1% to 5% of their bits are specified (care)bits. The rest are don’t-cares, which can take on anyvalue with no impact on the fault coverage. A test cubeis a deterministic test vector in which the bits that ATPGdoes not assign are left as don’t-cares (that is, the ATPGdoes not randomly fill the