Tutorial Survey of Test Vector Compression Techniques Nur A Touba University of Texas at Austin tester However achieving high fault coverage with stand alone BIST generally requires considerable overhead because of random pattern resistant RPR faults which have low detection probabilities Detecting such faults requires either test points or deterministic pattern embedding logic Other issues with BIST include the need for a BIST ready design a way to handle false and multicycle paths and the need to keep nondeterministic values from corrupting the nal signature Test data compression consists of test vector compression on the input side and response compaction on the output side Test vector compression has been an active area of research yielding a wide variety of techniques This article summarizes and categorizes these techniques explaining how they relate to one another The goal is to provide a framework for understanding the theory and research in this area THE AMOUNT OF DATA required to test ICs is growing rapidly in each new generation of technology Increasing integration density results in larger designs with more scan cells and more faults Moreover achieving high test quality in ever smaller geometries requires more test patterns targeting delay faults and other fault models beyond stuckat faults Conventional external testing involves storing all test vectors and test response on an external tester that is ATE But these testers have limited speed memory and I O channels The test data bandwidth between the tester and the chip is relatively small in fact it is often the bottleneck determining how fast you can test the chip Testing cannot proceed any faster than the amount of time required to transfer the test data Test time amount of test data on tester number of tester channels tester clock rate Overcoming limited tester chip bandwidth Three general approaches help overcome this bottleneck stand alone BIST hybrid BIST and test data compression Stand alone BIST Traditional stand alone BIST involves using on chip hardware to perform all test pattern generation and output response analysis Stand alone BIST eliminates the need for tester storage This is very useful for performing self test in the field when there is no access to a 294 0740 7475 06 20 00 2006 IEEE Hybrid BIST If a particular chip design uses BIST only for manufacturing test then hybrid BIST can be more cost effective than stand alone BIST Hybrid BIST involves storing some data on the tester to help detect RPR faults The simplest approach is to perform ATPG for RPR faults not detected by pseudorandom BIST to obtain a set of deterministic test patterns that top up the fault coverage to the desired level and then store those patterns directly on the tester More ef cient hybrid BIST schemes store the deterministic top up patterns on the tester in a compressed form then use the existing BIST hardware to decompress these patterns Some schemes embed deterministic patterns by using compressed weight sets or by perturbing the pseudorandom sequence in some manner Test data compression As Figure 1 illustrates test data compression involves adding some additional on chip hardware before and after the scan chains This additional hardware decompresses the test stimulus coming from the tester it also compacts the response after the scan chains and before it goes to the tester This permits storing the test data in a compressed form on the tester With test data compression the tester still applies a precise deterministic ATPG generated test set to the circuit under test CUT Copublished by the IEEE CS and the IEEE CASS IEEE Design Test of Computers This process differs from that of hybrid BIST which applies a large number of patterns including both pseudorandom and deterministic data Although hybrid BIST can reduce the amount of test data on the tester more than test data compression can hybrid BIST generally requires longer test application time because you must apply more patterns to the CUT than with test data compression in essence hybrid BIST trades off more test application time for less tester storage The advantage of test data compression is that it generates the complete set of patterns applied to the CUT with ATPG and this set of test patterns is optimizable with respect to the desired fault coverage Test data compression is also easier to adopt in industry because it s compatible with the conventional design rules and test generation ows for scan testing Test data compression provides two benefits First it reduces the amount of data stored on the tester which can extend the life of older testers that have limited memory Second and this is the more important bene t which applies even for testers with plenty of memory it can reduce the test time for a given test data bandwidth Doing so typically involves having the decompressor expand the data from n tester channels to ll greater than n scan chains Increasing the number of scan chains shortens each scan chain in turn reducing the number of clock cycles needed to shift in each test vector Test data compression must compress the test vectors losslessly that is it must reproduce all the care bits after decompression to preserve fault coverage The output response on the other hand can use lossy compaction which does not reproduce all data losing information with negligible impact on fault coverage Ideally the output response could be compacted using just a multiple input signature register MISR However any unknown nondeterministic values in the output response would corrupt the nal signature Researchers have developed several schemes to address the problem of unknown values in the output response including eliminating the source of the unknown values selectively masking the unknown values in the output stream or using an output compaction scheme that can tolerate the unknown values Output compaction is an entire subject in itself and I will not discuss it further in this article The subject here is test vector compression techniques Test vectors are highly compressible because typically only 1 to 5 of their bits are speci ed care bits The rest are don t cares which can take on any July August 2006 Compressed test stimulus Chip Decompressor Tester Compactor Compacted output response Figure 1 Test data compression value with no impact on the fault coverage A test cube is a deterministic test vector in which the bits that ATPG does not assign are left as don t cares that is the