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Duke ECE 269 - Delay Test

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1ECE 269Krish Chakrabarty1EE 269VLSI System TestingKrish ChakrabartyLecture 17:Delay TestECE 269Krish Chakrabarty2Delay Test• Delay test definition• Circuit delays and event propagation• Path-delay tests Non-robust test Robust test Five-valued logic and test generation• Path-delay fault (PDF) and other fault models• Test application methods Combinational, enhanced-scan and normal-scan Variable-clock and rated-clock methods• At-speed test• Timing design and delay test• Summary2ECE 269Krish Chakrabarty3Delay Test Definition• A circuit that passes delay test must produce correct outputs when inputs are applied and outputs observed with specified timing.• For a combinational or synchronous sequential circuit, delay test verifies the limits of delay in combinational logic.• Delay test problem for asynchronous circuits is complex and not well understood.ECE 269Krish Chakrabarty4Digital Circuit TimingInputInputInputInputSignalSignalSignalSignalchangeschangeschangeschangesInputsInputsInputsInputsOutputsOutputsOutputsOutputstimetimetimetimeTransientTransientTransientTransientregionregionregionregionClock periodClock periodClock periodClock periodComb.Comb.Comb.Comb.logiclogiclogiclogicOutputOutputOutputOutputObservationObservationObservationObservationinstantinstantinstantinstantSynchronizedSynchronizedSynchronizedSynchronizedWith clockWith clockWith clockWith clock3ECE 269Krish Chakrabarty5Circuit Delays• Switching or inertial delay is the interval between input change and output change of a gate: Depends on input capacitance, device (transistor) characteristics and output capacitance of gate. Also depends on input rise or fall times and states of other inputs (second-order effects). Approximation: fixed rise and fall delays (or min-max delay range, or single fixed delay) for gate output.• Propagation or interconnect delay is the time a transition takesto travel between gates: Depends on transmission line effects (distributed R, L, Cparameters, length and loading) of routing paths. Approximation: modeled as lumped delays for gate inputs.• See Section 5.3.5 for timing models.ECE 269Krish Chakrabarty6Event Propagation Delays2 4 611 353100022Path P1P2P3Single lumped inertial delay modeled for each gatePI transitions assumed to occur without time skew4ECE 269Krish Chakrabarty7Circuit Outputs• Each path can potentially produce one signal transition at the output.• The location of an output transition in time is determined by the delay of the path.Initial valueInitial valueFinal valueFinal valueClock periodFast transitionsSlow transitionstimeECE 269Krish Chakrabarty8Singly-Testable Paths(Non-Robust Test)• The delay of a target path is tested if the test propagates a transition via path to a path destination.• Delay test is a combinational vector-pair, V1,V2, that: Produces a transition at path input. Produces static sensitization -- All off-path inputs assume non-controlling states in V2.V1 V2V1 V2Static sensitization guarantees a test when the target path is theonly faulty path. The test is, therefore, called non-robust. It is a test with minimal restriction. A path with no such test is a false path.TargetpathOff-path inputsdon’tcare5ECE 269Krish Chakrabarty9Robust Test• A robust test guarantees the detection of a delay fault of the target path, irrespective of delay faults on other paths.• A robust test is a combinational vector-pair, V1, V2, that satisfies following conditions:• Produce real events (different steady-state values for V1 and V2) on all on-path signals.• All on-path signals must have controlling events arriving via the target path.• A robust test is also a non-robust test.• Concept of robust test is general – robust tests for other fault models can be defined.ECE 269Krish Chakrabarty10Path-Delay Faults (PDF)• Two PDFs (rising and falling transitions) for each physical path.• Total number of paths is an exponential function of gates. Critical paths, identified by static timing analysis (e.g., Primetime from Synopsys), must be tested.• PDF tests are delay-independent. Robust tests are preferred, but some paths have only non-robust tests.6ECE 269Krish Chakrabarty11Other Delay Fault Models• Segment-delay fault -- A segment of an I/O path is assumed to have large delay such that all paths containing the segment become faulty.• Transition fault -- A segment-delay fault with segment of unit length (single gate): Two faults per gate; slow-to-rise and slow-to-fall. Tests are similar to stuck-at fault tests. For example, a line is initialized to 0 and then tested for s-a-0 fault to detect slow-to-rise transition fault. Models spot (or gross) delay defects.• Line-delay fault – A transition fault tested through the longest delay path. Two faults per line or gate. Tests are dependent on modeled delays of gates.• Gate-delay fault – A gate is assumed to have a delay increase of certain amount (called fault size) while all other gates retain some nominal delays. Gate-delay faults only of certain sizes may be detectable.ECE 269Krish Chakrabarty12Slow-Clock TestInputInputInputInputtest clocktest clocktest clocktest clockOutputOutputOutputOutputtest clocktest clocktest clocktest clockCombinationalCombinationalCombinationalCombinationalcircuitcircuitcircuitcircuitInputInputInputInputlatcheslatcheslatcheslatchesOutputOutputOutputOutputlatcheslatcheslatcheslatchesInputtest clockOutputtest clockV1appliedV2appliedOutputlatchedTestclockperiodRatedclockperiod7ECE 269Krish Chakrabarty13Enhanced-Scan TestCombinationalcircuitHLSFFHLSFFPIPOSCANINSCAN-OUTHOLDCK TCCK TCCK: system clockTC: test controlHOLD: hold signalSFF: scan flip-flopHL: hold latchCKHOLDCKperiodNormalmodeTCScan modeV1 PIappliedV2 PIappliedScaninV1statesScaninV2 statesV1 settlesResultlatchedScanoutresultECE 269Krish Chakrabarty14Normal-Scan TestCombinationalcircuitSFFSFFPIPOSCANINSCAN-OUTCK TCCK TCCK: system clockTC: test controlSFF: scan flip-flopRatedCK periodNormalmodeTC(A)Scan modeV1 PIsappliedV2 PIsappliedScaninV1 statesResultlatchedResultscanoutV2 states generated, (A) by one-bit scan shift of V1, or(B) by V1 applied in functional mode.Scan modeNormal modeTC(B)Scan modeScan modeSlow CKperiodtGen. V2statesPathtestedSlow clock8ECE 269Krish Chakrabarty15Variable-Clock Sequential TestT 1 PIPOT n-2 PIPOT n-1 PIPOT n+1PIPOT n+mPIPO121122T n PIPOInitialization sequence(slow


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