IEEE TRANSACTIONS ON COMPUTER AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS VOL 20 NO 3 MARCH 2001 355 System on a Chip Test Data Compression and Decompression Architectures Based on Golomb Codes Anshuman Chandra Student Member IEEE and Krishnendu Chakrabarty Senior Member IEEE Abstract We present a new test data compression method and decompression architecture based on variable to variable length Golomb codes The proposed method is especially suitable for encoding precomputed test sets for embedded cores in a system on a chip SoC The major advantages of Golomb coding of test data include very high compression analytically predictable compression results and a low cost and scalable on chip decoder In addition the novel interleaving decompression architecture allows multiple cores in an SoC to be tested concurrently using a single automatic test equipment input output channel We demonstrate the effectiveness of the proposed approach by applying it to the Internaional Symposium on Circuits and Systems benchmark circuits and to two industrial production circuits We also use analytical and experimental means to highlight the superiority of Golomb codes over run length codes Index Terms Automatic test equipment ATE decompression architecture difference vector embedded core testing precomputed test sets test set encoding testing time variable to variable length codes I INTRODUCTION C ORE BASED system on a chip SoC designs present a number of test challenges 1 These chips are composed of several reusable intellectual property IP cores that together integrate a wide range of functionality on a single die The volume of test data for an SoC is growing rapidly as IP cores become more complex and an increasing number of these cores are being integrated in a chip In order to effectively test these systems each core must be adequately exercised with a set of precomputed test patterns provided by the core vendor Fig 1 However the input output I O channel capacity speed and accuracy and data memory of automatic test equipment ATE are limited Thus it is becoming increasingly difficult to apply the enormous volume of test data to the SoC which can be as high as 2 5 Gb for an industrial application specific integrated circuit 2 without increasing testing time and test cost substantially The reduction in test data volume will not only reduce ATE memory requirements but also lower testing time The testing Manuscript received August 1 2000 This work was supported in part by the National Science Foundation under Grant CCR 9875324 by a contract from Delphi Delco Electronics Systems and by an equipment grant from Sun Microsystems This paper was presented in part at the VLSI Test Symposium Montreal QB Canada May 2000 This paper was recommended by Associate Editor R Karri A Chandra and K Chakrabarty are with the Department of Electrical and Computer Engineering Duke University Durham NC 27708 USA e mail krish ee duke edu Publisher Item Identifier S 0278 0070 01 01508 1 Fig 1 Conceptual architecture for testing an SoC time of an SoC depends on the test data volume the time required to transfer the data to the cores the rate at which the test data is transferred measured by the cores test data bandwidth and ATE channel capacity and the maximum scan chain length The total test time can be reduced by either reducing the test data volume or by shortening and reorganizing the scan chains While test data volume reduction techniques can be applied to both hard and soft cores scan chains cannot be modified in hard cores Lower testing time will increase production capacity as well as reduce test cost and time to market for SoCs Therefore new techniques are needed for decreasing test data volume in order to overcome memory bottlenecks and to reduce testing time Built in self test BIST has emerged as a useful approach for alleviating the above problems 3 BIST reduces dependencies on expensive ATEs and it allows precomputed test sets to be embedded in test sequences generated by BIST hardware 4 6 However BIST can be applied directly to SoC designs only if the embedded cores are BIST ready Since most IP cores that are currently available from core vendors are not BIST ready considerable redesign is necessary for incorporating BIST This increases time to market and therefore defeats the very purpose of using IP cores Test data compression offers a promising solution to the problem of reducing the test data volume for SoCs especially if the IP cores in the system are not BIST ready 7 10 13 for an IP 14 In this approach a precomputed test set core is compressed encoded to a much smaller test set which is stored in ATE memory An on chip decoder is used from during test for pattern decompression to obtain application Fig 2 0278 0070 01 10 00 2001 IEEE 356 IEEE TRANSACTIONS ON COMPUTER AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS VOL 20 NO 3 MARCH 2001 Fig 3 Decompression architecture based on a CSR Fig 2 Conceptual architecture for testing an SoC by storing the encoded test data T in ATE memory and decoding it using on chip decoders Test data compression using statistical coding of test sequences for synchronous sequential nonscan circuits was presented in 7 and 8 Statistical coding was successfully applied to test sets for full scan circuits in 9 While the compression method in 7 and 8 is restricted to sequential circuits with a large number of flip flops and relatively few primary inputs the work presented in 9 does not conclusively demonstrate that statistical coding provides greater compression than standard automatic test pattern generation ATPG compression methods for full scan circuits 11 12 Test data compression was also employed in 13 and 14 to reduce the time needed to download test patterns across a network to a user interface workstation attached to an ATE This method employs a combination of Burrows Wheeler BW transformation and run length coding The encoding and decoding algorithm are implemented entirely in software A hardware implementation of the BW decoder is prohibitively complex thus other methods are required for efficient test data compression and on chip decompression An alternative approach to test data compression is motivated by the fact that successive test patterns in a test sequence often differ in only a small number of bits This was exploited in a dif 10 where instead of compressing the test sequence determined from was comference vector sequence contains few ones pressed using run