1Wafer-Level Test-During-Burn-In&Industrial DFT practices: A primerSudarshan BahukudumbiECE 269: March 27th2008Certain figures obtained from: www.edn.com/article/CA46604.html www.aehr.com• Ever-increasing demand for high device reliability and low defect-per-million levels• Reliability screening routinely performed before product is shipped to the customer• Burn-in → widely used reliability screening techniqueIntroductionhttp://www.aehr.com/2Wafer-level test-during-burn-in• Wafer level burn-in has recently emerged as a promising technique to minimize burn-in cost• Test during burn-in at the wafer level → easier and less expensive method to identify faulty devices• We refer to this process as “wafer-level test-during-burn-in” (WLTBI)• Increasing demand for “known good die” highlights need for cost-effective WLTBI solutionsComparing burn-in flowsPackage level burn-inWafer-level test-during-burn-in(WLTBI)3Commercial WLTBI Equipmenthttp://www.aehr.com/products/fox_14_data_sheet.pdfAEHR FOX 14: Full Wafer Contact Burn-in and Test System• AEHR FOX 14:– Contact 14 wafers simultaneously – 30,000 contact-point capability per wafer– Full algorithmic test for memories– Vector pattern generator for devices using BIST• Motorola teamed up with Tokyo Electron Ltd. and W.L. Gore & Associates Inc. to develop a WLTBI system for commercial use• Similar equipment with response monitoring capabilities at elevated temperatures deployed by Advantest and Delta-V systemsMotivation• Successful WLTBI requires thorough understanding of device thermal characteristics• Accurate burn-in predictions → junction temperatures need to be maintained within a small envelope • Junction temperature (Tj) function of P, ambient temperature (Ta) and thermal resistance (θja)• Controlling power consumption during test therefore critical for WLTBITj= Ta+ P.θja4Test timePower dissipationPBIFixed value of device power considered for modeling time req. for burn-in  Device subjected to under burn-in Results in test escape of latent defects Device subjected to over burn-in Results in yield loss Can lead to thermal runawayWLTBI of core-based SoCs: ChallengesThermal runaway on a packaged 90nm ICAcceptable marginTest Scheduling: Motivation• Objective of dynamic burn-in is to have the maximum switching activity– Testing a single core at a time (best thermal scenario) does not contribute significantly towards stressing the device– Ineffective screening of latent defects• Not all burn-in time is for test!– Burn-in involves multiple temperature and voltage cycling– Long periods of static burn-in• All die in the wafer cannot be contacted during WLTBI– Lack on sufficient probe pins – Limitations of WLTBI equipment to remove heat5Metrics: variation in power consumption1) Statistical variance in test power: If TSoCis the test time for the SoC in clock cycles, and Pmeanthe mean value of power consumption per clock cycle the variance is:2) Cycle-to-cycle variation: Indicator of the “flatness” in the power profile quantified using: PCore_Assign: Core-ordering problem for WLTBIObjective: determine optimal ordering of cores such that:– Variation in power consumption is minimized– Constraint on peak power is satisfiedProblem PCore_Assign: Let T1, T2and T3be the sets of cores on TAM partitions 1, 2 and 3 respectively. Determine the sets of cores that can be tested simultaneously, and the ordering of the cores on the TAM partitions, such that the overall variation in power consumption for the SoC is minimized and the peak power constraint Pmaxis satisfied.• PCore_Assignis NP-Complete - Efficient heuristics therefore necessary6Core_Order Heuristic Initial_Assign: Initial assignment of cores. Determine triple with lowest ρ(i,j,k)init Assign_Cores: Iteratively assign cores in sets of three to the test schedule. Exhaust all valid triple assignments Unmatched_Assign: Assigns remaining cores to minimize power variation during test The worst-case time complexity of the heuristic procedure in terms of the of B is O(NB); B is the number of TAM partitions ρ(i,j,k) → variation in power consumption when cores i, j, and k tested in parallelBeginConstruct finaltest scheduleGather cycle-accurate power dataAssign initial set of three coresIteratively assign cores In sets of threeAssign remaining coresExample TAM architecture and corresponding schedule10 core d695 SoC with W=32Corresponding testschedule7Baseline methods1) The first baseline method solves a power-constrained test-scheduling problem for core-based SoCs• Same architecture as Core_Order heuristic• Single power limit for entire SoC• Similar to [Samii_ITC06]2) No two cores are tested concurrently in baseline method 2- Division of W TAM wires into B TAM partitions, and the assignment of cores to TAM partitions are determined a prioriS. Samii, et al., "Cycle-accurate test power modeling and its application to SOC test scheduling", Proc. ITC, 2006.Experimental ResultsTest power variation: d695 versus Baseline 18Power profile (d695): Core_Orderheuristic versus Baseline1Cycle-accurate power consumption11011101Clock Cycle234560 1 1 0 1 1 0FF1FF2FF3FF4FF5FF6Scan in Scan out110110111101001Clock Cycle234560 1 1 0 1 1 0 1 1 0 1 1 FF1FF2FF3FF4FF5FF6Scan in Scan out11110101011101110110011Clock Cycle234560 1 1 0 1 1 0 1 1 0 1 1 1 1 0 1 FF1FF2FF3FF4FF5FF6Scan in Scan out1111110101101011011110011100111Clock Cycle234560 1 1 0 1 1 0 1 1 0 1 1 1 1 0 1 1 1 0 FF1FF2FF3FF4FF5FF6Scan in Scan out11101110101110101110101110101110001111Clock Cycle234560 1 1 0 1 1 0 1 1 0 1 1 1 1 0 1 1 1 0 1 1 FF1FF2FF3FF4FF5FF6Scan in Scan out1110111110101101010111101011110100111010011101Clock Cycle234560 1 1 0 1 1 0 1 1 0 1 1 1 1 0 1 1 1 0 1 1 1 FF1FF2FF3FF4FF5FF6Scan in Scan out11101111111010110110101101101011111010101110100011101Clock Cycle234560 1 1 0 1 1 0 1 1 0 1 1 1 1 0 1 1 1 0 1 1 1 FF1FF2FF3FF4FF5FF6Scan in Scan outNumber of transitions: 4Number of transitions: 5Cycle-by-cycle scan cell transitions = {4,4,4,4,5,4}Scan-based testing for WLTBI: Challenges?9PTPO: Test-pattern ordering problem for WLTBIObjective: determine optimal ordering of test patterns for WLTBI such that:– Variation in power