Wafer Level Test During Burn In Industrial DFT practices A primer Sudarshan Bahukudumbi ECE 269 March 27th 2008 Certain figures obtained from www edn com article CA46604 html www aehr com Introduction Ever increasing demand for high device reliability and low defect per million levels Reliability screening routinely performed before product is shipped to the customer Burn in widely used reliability screening technique http www aehr com 1 Wafer level test during burn in Wafer level burn in has recently emerged as a promising technique to minimize burn in cost Test during burn in at the wafer level easier and less expensive method to identify faulty devices We refer to this process as wafer level test during burn in WLTBI Increasing demand for known good die highlights need for cost effective WLTBI solutions Comparing burn in flows Wafer level test during burn in Package level burn in WLTBI 2 Commercial WLTBI Equipment AEHR FOX 14 Contact 14 wafers simultaneously 30 000 contact point capability per wafer Full algorithmic test for memories Vector pattern generator for devices using BIST Motorola teamed up with Tokyo Electron Ltd and W L Gore Associates Inc to develop a WLTBI system for commercial use Similar equipment with response monitoring capabilities at elevated temperatures deployed by Advantest and Delta V systems AEHR FOX 14 Full Wafer Contact Burn in and Test System http www aehr com products fox 14 data sheet pdf Motivation Successful WLTBI requires thorough understanding of device thermal characteristics Accurate burn in predictions junction temperatures need to be maintained within a small envelope Junction temperature Tj function of P ambient temperature Ta and thermal resistance ja Tj Ta P ja Controlling power consumption during test therefore critical for WLTBI 3 WLTBI of core based SoCs Challenges Power dissipation Fixed value of device power considered for modeling time req for burn in PBI Device subjected to over burn in Results in yield loss Can lead to thermal Device subjected to runaway under burn in Results in test escape of latent defects Test time Acceptable margin Thermal runaway on a packaged 90nm IC Test Scheduling Motivation Objective of dynamic burn in is to have the maximum switching activity Testing a single core at a time best thermal scenario does not contribute significantly towards stressing the device Ineffective screening of latent defects Not all burn in time is for test Burn in involves multiple temperature and voltage cycling Long periods of static burn in All die in the wafer cannot be contacted during WLTBI Lack on sufficient probe pins Limitations of WLTBI equipment to remove heat 4 Metrics variation in power consumption 1 Statistical variance in test power If TSoC is the test time for the SoC in clock cycles and Pmean the mean value of power consumption per clock cycle the variance is 2 Cycle to cycle variation Indicator of the flatness in the power profile quantified using PCore Assign Core ordering problem for WLTBI Objective determine optimal ordering of cores such that Variation in power consumption is minimized Constraint on peak power is satisfied Problem PCore Assign Let T1 T2 and T3 be the sets of cores on TAM partitions 1 2 and 3 respectively Determine the sets of cores that can be tested simultaneously and the ordering of the cores on the TAM partitions such that the overall variation in power consumption for the SoC is minimized and the peak power constraint Pmax is satisfied PCore Assign is NP Complete Efficient heuristics therefore necessary 5 Core Order Heuristic Begin Gather cycle accurate power data Assign initial set of three cores Iteratively assign cores In sets of three Assign remaining cores Construct final test schedule Initial Assign Initial assignment of cores Determine triple with lowest i j k init Assign Cores Iteratively assign cores in sets of three to the test schedule Exhaust all valid triple assignments Unmatched Assign Assigns remaining cores to minimize power variation during test The worst case time complexity of the heuristic procedure in terms of the of B is O NB B is the number of TAM partitions i j k variation in power consumption when cores i j and k tested in parallel Example TAM architecture and corresponding schedule 10 core d695 SoC with W 32 Corresponding test schedule 6 Baseline methods 1 The first baseline method solves a power constrained test scheduling problem for core based SoCs Same architecture as Core Order heuristic Single power limit for entire SoC Similar to Samii ITC06 2 No two cores are tested concurrently in baseline method 2 Division of W TAM wires into B TAM partitions and the assignment of cores to TAM partitions are determined a priori S Samii et al Cycle accurate test power modeling and its application to SOC test scheduling Proc ITC 2006 Experimental Results Test power variation d695 versus Baseline 1 7 Power profile d695 Core Order heuristic versus Baseline1 Cycle accurate power consumption Clock Cycle Scan in FF1 FF2 FF3 FF4 FF5 FF6 Scan out 0 1 1 0 1 1 0 1 0 1 1 1 0 1 1 1 0 1 1 0 1 0 1 1 1 0 2 1 1 0 1 1 0 1 0 1 1 1 3 1 1 0 1 1 0 1 0 1 4 1 1 0 1 1 0 1 0 1 5 1 1 0 1 1 0 1 0 1 1 0 1 1 0 6 1 Number of transitions 45 Cycle by cycle scan cell transitions 4 4 4 4 5 4 Scan based testing for WLTBI Challenges 8 PTPO Test pattern ordering problem for WLTBI Objective determine optimal ordering of test patterns for WLTBI such that Variation in power consumption is minimized Constraint on peak power is satisfied Problem PTPO Given a test set T T1 T2 TN determine an ordering of test patterns such that the a overall variation in power consumption is minimized and the peak power constraint Pmax is satisfied PTPO is NP Complete Efficient heuristics therefore necessary Industrial DFT practices A primer f o r Material for slides www edn com article CA46604 html 9 Scan design recap Circuit with no scan Scan enabled circuit 3 additional pins Scan path Need for Lockup Latch Undesirable effect of data transfer between two flops in a single clock cycle 10 Lockup Latch Adds half a cycle of delay Needs to be transparent when the clock is in the low period For falling edge FFs latch transparent when clock is high Designs with E and E FF s E after E in a scan chain Single clock cycle will scan data through both flops Place all E at the beginning of the scan chain Why Lockup latch prevents data from shifting in one clock cycle 11 Scan design multiple clocks Multiple clock domains one scan chain for