1ECE 269Krish Chakrabarty1ECE 269VLSI System TestingKrish ChakrabartyLecture 13:Design for Testability (DFT): 1ECE 269Krish Chakrabarty2Outline• Motivation and Goals• Controllability and Observability• Ad Hoc DFT Methods– Control/Test Point Insertion– Circuit restructuring– Timing considerations2ECE 269Krish Chakrabarty3Why Design for Test?• Test generation is complex (NP-complete), limiting exact application to circuits of moderate complexity• Random logic circuits containing, say 106or more gates, or 103or more flip-flops may be too large for ATPG• Heuristic methods generally used for testing complex circuits, e.g. microprocessors or high-density RAM chips. – The fault coverage of such methods is low and hard to determine• To ensure high testability, design for testability (DFT)needed.• Make circuits easy to test by designECE 269Krish Chakrabarty4Testability Definitions (Keiner 1980)Testability“A design characteristic which allows the status (operable, non-operable, or degraded) of a unit to be determined in a timely manner”Design for Testability (DFT)“A design process such that deliberate effort is expendedto assure that a product may be thoroughly tested with minimum effort and cost, and that high confidence may be ascribed to the test results”3ECE 269Krish Chakrabarty5Testability Goals• Maximize fault coverage• Minimize test application time• Minimize test data volume• Minimize test generation effort• Maximize fault resolution (isolating fault to smallest replaceable component)• Minimize hardware/software overhead needed for testing• Make the system as much self-testing as possibleECE 269Krish Chakrabarty6Design and Test Flow: Old View• Test is merely an afterthoughtSpecificationDesignDesignerrorsFabricationTestingRandomdefectsSynthesis, full-customsimulation, verification,test generationAccept RejectPassFail4ECE 269Krish Chakrabarty7“Brick Wall” Between Design and TestDesignTestECE 269Krish Chakrabarty8Design and Test Flow: New View• Design and test are tightly coupledSpecificationDesign fortestabilityDesignerrorsFabricationTestingRandomdefectsAccept RejectPassFailProcessimprovementsDesignimprovementsDiagnosis5ECE 269Krish Chakrabarty9Definition• Design for testability (DFT) refers to those design techniques that make test generation and test application cost-effective.• DFT methods for digital circuits:– Ad-hoc methods– Structured methods:• Scan• Partial Scan• Built-in self-test (BIST)• Boundary scan• DFT method for mixed-signal circuits:• Analog test busECE 269Krish Chakrabarty10Ad-Hoc DFT Methods• Good design practices learnt through experience are used as guidelines:• Avoid asynchronous (unclocked) feedback.• Make flip-flops initializable.• Avoid redundant gates. Avoid large fanin gates.• Provide test control for difficult-to-control signals.• Avoid gated clocks.• Consider ATE requirements (tristates, etc.)• Design reviews conducted by experts or design auditing tools.• Disadvantages of ad-hoc DFT methods:• Experts and tools not always available.• Test generation is often manual with no guarantee of high fault coverage.• Design iterations may be necessary.6ECE 269Krish Chakrabarty11Impact of Testing MethodConsider testing a large combinational circuit. The preciseimpact of each testing method depends on the circuit size,circuit complexity, and practical design constraints Testability parameter PODEM Exhaustive RandomFault coverage good best worstTest application time good worst fairTest data length best worst fairTest generation effort worst best goodSuitability for self-test bad fair goodTesting methodECE 269Krish Chakrabarty12Testability Factors• Compute controllability and observability values for all signal nodes in the circuit• “Bad” values can pinpoint hard-to-test areas of the circuit that need redesign• Computation effort should be small, e.g., 10% of test generation effort. (Implies use of heuristics)Controllability and Observability7ECE 269Krish Chakrabarty13Controllability and Observability• Several related schemes have been proposed, e.g.– TIMEAS (Stephenson and Grason, 1976)– SCOAP (Goldstein, 1979)• Interpretation of controllability/observabilityvalues is difficult• Often unclear how to modify circuit to improve specific controllability/observability values• Systematic DFT can provide high levels a prioriECE 269Krish Chakrabarty14Control/Test Point Insertion• Make hard-to-control internal signals controllable via extra primary inputs and logic (control points)• Make hard-to-observe internal signals observable via extra primary outputs and logic (test points)UncontrollablesignalUnobservablesignalyyy*yxy* = y when x = ayz8ECE 269Krish Chakrabarty15Control/Test PointsSite Selection• Memory elements determining a system’s control states• Long narrow subcircuits with buried components• Short wide subcircuits with high fan-in or fan-out• Internal system buses• Redundant circuits containing undetectable faults• Circuit bottlenecks determined by programs such as SCOAPMajor Limitations• Availability of spare I/O pins• Cost of added test/control circuitsECE 269Krish Chakrabarty16Circuit Restructuringn-bit counterz1z2znCountStage 1k-bitcounterz1z2zkx1CountStage 1k-bitcounterz1z2zkx2Control points9ECE 269Krish Chakrabarty17XOR-Based Designs• Circuits composed exclusively of XOR (and XNOR) are easy to test– Easy to observe– Easy to control• Every all-XOR/XNOR circuit composed of 2-input XOR gates can be tested for all SSL faults with 3 test patterns (Homework problem!)• Every all-XOR/XNOR circuit composed of 2-input XOR gates can be tested for all cell faults with 4 test patterns101010010011100100111010011001010011ECE 269Krish Chakrabarty18Reed-Muller Circuits• Every Boolean function can be expressed in the “Reed-Muller” form consisting of an XOR sum of product terms with no complementationExample:f(x1,x2,x3,x4) = 1 ⊕ x1x2⊕ x1x3 ⊕ x1x2x3⊕ x2x3x4fx1x2x4x3x0 = 110ECE 269Krish Chakrabarty19Reed-Muller Circuits•An n-input Reed-Muller circuit can be tested for all SSL faults using n+4 tests patterns• It requires an extra AND gate, a control input and a test point• The number of gates and the circuit delay grows exponentially with n.f = a + b= ab + ab + ab= ab ⊕ ab ⊕ ab (sum of minterms)= ab ⊕ (1 ⊕ a)b ⊕ a(1 ⊕ b)= ab ⊕ b ⊕ ab ⊕ a ⊕ ab = a ⊕ b ⊕ abECE 269Krish