ECE 269 VLSI System Testing Krish Chakrabarty Lecture 13 Design for Testability DFT 1 ECE 269 Krish Chakrabarty 1 Outline Motivation and Goals Controllability and Observability Ad Hoc DFT Methods Control Test Point Insertion Circuit restructuring Timing considerations ECE 269 Krish Chakrabarty 2 1 Why Design for Test Test generation is complex NP complete limiting exact application to circuits of moderate complexity Random logic circuits containing say 106 or more gates or 103 or more flip flops may be too large for ATPG Heuristic methods generally used for testing complex circuits e g microprocessors or high density RAM chips The fault coverage of such methods is low and hard to determine To ensure high testability design for testability DFT needed Make circuits easy to test by design ECE 269 Krish Chakrabarty 3 Testability Definitions Keiner 1980 Testability A design characteristic which allows the status operable non operable or degraded of a unit to be determined in a timely manner Design for Testability DFT A design process such that deliberate effort is expended to assure that a product may be thoroughly tested with minimum effort and cost and that high confidence may be ascribed to the test results ECE 269 Krish Chakrabarty 4 2 Testability Goals Maximize fault coverage Minimize test application time Minimize test data volume Minimize test generation effort Maximize fault resolution isolating fault to smallest replaceable component Minimize hardware software overhead needed for testing Make the system as much self testing as possible Krish Chakrabarty ECE 269 5 Design and Test Flow Old View Test is merely an afterthought Specification Design errors Design Random defects Fabrication Synthesis full custom simulation verification test generation Testing Pass Accept ECE 269 Fail Reject Krish Chakrabarty 6 3 Brick Wall Between Design and Test Design Test Krish Chakrabarty ECE 269 7 Design and Test Flow New View Design and test are tightly coupled Specification Design errors Design for testability Design improvements Random defects Fabrication Process improvements Testing Diagnosis Pass Accept ECE 269 Krish Chakrabarty Fail Reject 8 4 Definition Design for testability DFT refers to those design techniques that make test generation and test application cost effective DFT methods for digital circuits Ad hoc methods Structured methods Scan Partial Scan Built in self test BIST Boundary scan DFT method for mixed signal circuits Analog test bus Krish Chakrabarty ECE 269 9 Ad Hoc DFT Methods Good design practices learnt through experience are used as guidelines Avoid asynchronous unclocked feedback Make flip flops initializable Avoid redundant gates Avoid large fanin gates Provide test control for difficult to control signals Avoid gated clocks Consider ATE requirements tristates etc Design reviews conducted by experts or design auditing tools Disadvantages of ad hoc DFT methods Experts and tools not always available Test generation is often manual with no guarantee of high fault coverage Design iterations may be necessary ECE 269 Krish Chakrabarty 10 5 Impact of Testing Method Consider testing a large combinational circuit The precise impact of each testing method depends on the circuit size circuit complexity and practical design constraints Testability parameter PODEM Fault coverage Test application time Test data length Test generation effort Suitability for self test good good best worst bad ECE 269 Testing method Exhaustive best worst worst best fair Random worst fair fair good good Krish Chakrabarty 11 Testability Factors Controllability and Observability Compute controllability and observability values for all signal nodes in the circuit Bad values can pinpoint hard to test areas of the circuit that need redesign Computation effort should be small e g 10 of test generation effort Implies use of heuristics ECE 269 Krish Chakrabarty 12 6 Controllability and Observability Several related schemes have been proposed e g TIMEAS Stephenson and Grason 1976 SCOAP Goldstein 1979 Interpretation of controllability observability values is difficult Often unclear how to modify circuit to improve specific controllability observability values Systematic DFT can provide high levels a priori Krish Chakrabarty ECE 269 13 Control Test Point Insertion Make hard to control internal signals controllable via extra primary inputs and logic control points Make hard to observe internal signals observable via extra primary outputs and logic test points y y y x y y when x a Uncontrollable signal y y z Unobservable signal ECE 269 Krish Chakrabarty 14 7 Control Test Points Site Selection Memory elements determining a system s control states Long narrow subcircuits with buried components Short wide subcircuits with high fan in or fan out Internal system buses Redundant circuits containing undetectable faults Circuit bottlenecks determined by programs such as SCOAP Major Limitations Availability of spare I O pins Cost of added test control circuits Krish Chakrabarty ECE 269 15 Circuit Restructuring z1 z2 n bit counter Count z1 z2 Count zk ECE 269 z1 z2 Stage 1 k bit counter Control points zn zk Stage 1 k bit counter x1 x2 Krish Chakrabarty 16 8 XOR Based Designs Circuits composed exclusively of XOR and XNOR are easy to test Easy to observe Easy to control Every all XOR XNOR circuit composed of 2 input XOR gates can be tested for all SSL faults with 3 test patterns Homework problem Every all XOR XNOR circuit composed of 2 input XOR gates can be tested for all cell faults with 4 test patterns 1010 1001 1001 0011 0011 0110 0101 0011 1010 Krish Chakrabarty ECE 269 17 Reed Muller Circuits Every Boolean function can be expressed in the ReedMuller form consisting of an XOR sum of product terms with no complementation Example f x1 x2 x3 x4 1 x1x2 x1x3 x1x2x3 x2x3x4 x1 x2 x3 x4 f x0 1 ECE 269 Krish Chakrabarty 18 9 Reed Muller Circuits An n input Reed Muller circuit can be tested for all SSL faults using n 4 tests patterns It requires an extra AND gate a control input and a test point The number of gates and the circuit delay grows exponentially with n f a b ab ab ab ab ab ab sum of minterms ab 1 a b a 1 b ab b ab a ab a b ab ECE 269 Krish Chakrabarty 19 Design Rules Summary Design controllable e g initializable and controllable circuits with careful selection of control test points Partition large hard to test circuits into small testable components Allow feedback paths to be opened and closed Avoid redundancy or