ECE 538 VLSI System Testing Krish Chakrabarty Fault Simulation Krish Chakrabarty ECE 538 1 Fault Simulation Problem and motivation Fault simulation algorithms Serial Parallel Deductive Concurrent Random Fault Sampling Summary ECE 538 Krish Chakrabarty 2 1 Problem and Motivation Fault simulation Problem Given A circuit A sequence of test vectors A fault model Determine Fault coverage fraction or percentage of modeled faults detected by test vectors Set of undetected faults Motivation Determine test quality and in turn product quality Find undetected fault targets to improve tests ECE 538 Krish Chakrabarty 3 Motivation Simulate a circuit in the presence of faults Given test set T determine the fault coverage of T test grading Fraction of faults percentage detected by T How is fault coverage related to defect coverage and yield DL 1 Y1 d DL defect level Probability of shipping a defective chip Y yield d fault defect coverage e g if Y 0 5 99 fault coverage needed to achieve 0 01 defect level 95 fault coverage implies 0 035 defect level ECE 538 Krish Chakrabarty 4 2 Applications Evaluate effects criticality of faults Evaluate fault coverage of given test set Generate fault dictionaries for diagnosis Aid in test pattern generation Fault dropping Test set compaction Simulation based and random test generation Krish Chakrabarty ECE 538 5 Fault Simulator in a VLSI Design Process Verification input stimuli Verified design netlist Fault simulator Modeled fault list Remove tested faults Fault Low coverage Adequate Stop ECE 538 Test vectors Test compactor Test generator Krish Chakrabarty Delete vectors Add vectors 6 3 Use in Test Generation Generate initial T Select target fault Evaluate T No Sufficient fault coverage Modify T No more faults Generate test for target Yes Done Fault simulate Discard detected faults Done Krish Chakrabarty ECE 538 7 Fault Simulation Scenario Circuit model mixed level Mostly logic with some switch level for high impedance Z and bidirectional signals High level models memory etc with pin faults Signal states logic Two 0 1 or three 0 1 X states for purely Boolean logic circuits Four states 0 1 X Z for sequential MOS circuits Timing Zero delay for combinational and synchronous circuits Mostly unit delay for circuits with feedback ECE 538 Krish Chakrabarty 8 4 Fault Simulation Scenario continued Faults Mostly single stuck at faults Sometimes stuck open transition and path delay faults analog circuit fault simulators are not yet in common use Equivalence fault collapsing of single stuck at faults Fault dropping a fault once detected is dropped from consideration as more vectors are simulated fault dropping may be suppressed for diagnosis Fault sampling a random sample of faults is simulated when the circuit is large Krish Chakrabarty ECE 538 9 Fault Simulation Algorithms ECE 538 Serial Parallel Deductive Concurrent Krish Chakrabarty 10 5 Serial Algorithm Algorithm Simulate fault free circuit and save responses Repeat following steps for each fault in the fault list Modify netlist by injecting one fault Simulate modified netlist vector by vector comparing responses with saved responses If response differs report fault detection and suspend simulation of remaining vectors Advantages Easy to implement needs only a true value simulator less memory Most faults including analog faults can be simulated ECE 538 Krish Chakrabarty 11 Serial Algorithm Cont Disadvantage Much repeated computation CPU time prohibitive for VLSI circuits Alternative Simulate many faults together Test vectors Fault free circuit Comparator f1 detected Comparator f2 detected Comparator fn detected Circuit with fault f1 Circuit with fault f2 Circuit with fault fn ECE 538 Krish Chakrabarty 12 6 Parallel Fault Simulation Compiled code method best with two states 0 1 Exploits inherent bit parallelism of logic operations on computer words Storage one word per line for two state simulation Multi pass simulation Each pass simulates w 1 new faults where w is the machine word length Speed up over serial method w 1 Not suitable for circuits with timing critical and nonBoolean logic Krish Chakrabarty ECE 538 13 Parallel Fault Simulation Example Bit 0 fault free circuit Bit 1 circuit with c s a 0 Bit 2 circuit with f s a 1 1 1 1 c s a 0 detected 1 0 1 a 1 1 1 b 1 0 1 c e 1 0 1 s a 0 g 0 0 0 d ECE 538 f s a 1 Krish Chakrabarty 0 0 1 14 7 Limitations of Parallel Fault Simulation Useful for two 1 0 or three 0 1 X logic values not suitable for multiple logic values e g 0 1 U R F Multiple logic values can be handled but operations are complex Wasted computations Fault dropping not carried out effectively Not possible to discard faults that are in the same word ECE 538 Krish Chakrabarty 15 Deductive Fault Simulation One pass simulation Each line k contains a list Lk of faults detectable on k Following true value simulation of each vector fault lists of all gate output lines are updated using set theoretic rules signal values and gate input fault lists PO fault lists provide detection data Limitations Set theoretic rules difficult to derive for non Boolean gates Gate delays are difficult to use ECE 538 Krish Chakrabarty 16 8 Deductive Fault Simulation Example Notation Lk is fault list for line k kn is s a n fault on line k b0 c0 1 b0 e c f d b0 d0 1 0 b0 d0 f1 1 g U b Le La U Lc U e0 a0 b0 c0 e0 a0 11 a Lg Le Lf U g0 a0 c0 e0 g0 Faults detected by the input vector Krish Chakrabarty ECE 538 17 Fault List Propagation Consider an AND gate Z A B and let A B 1 Then LZ LA LB Z s a 0 Let A 0 and B 1 Then LZ LA LB Z s a 1 LA LB Z s a 1 In general let I be the set of inputs of gate Z with controlling value c and inversion i Let C be the set of inputs with value c if C then LZ Lj Z s a c i j I else LZ Lj Lj Z s a c i j C j I C If no input has value c then fault effect on an input propagates to output If some inputs have value c only faults that affect inputs with c not c propagates to output ECE 538 Krish Chakrabarty 18 9 Deductive Simulation Example a b c f j g h d m i k e Input vector 00110 Fault set after fault collapsing a 0 a 1 b 1 c 0 c 1 d 1 e 0 g 0 h 0 h 1 La a 1 Lb b 1 Lc c 0 Ld Le Lf La Lb Lg Lc g 0 c 0 g 0 Lh Lc h 0 c 0 h 0 Lj Lg Lf c 0 g 0 Li Ld Lh c 0 h 0 Lk Li Le c 0 h 0 Lm Lk Lj h 0 h 0 is detected Delete h 0 from fault lists Lh Li Lk and Lm ECE 538 Krish Chakrabarty 19 Concurrent Fault Simulation Event driven simulation …