ECE 269 VLSI System Testing Krish Chakrabarty Lecture 1 Overview ECE 269 Krish Chakrabarty 1 Lecture 1 Introduction VLSI realization process Verification and test Ideal and real tests Costs of testing Roles of testing A modern VLSI device system on a chip Course outline Part I Introduction to testing Part II Test methods Part III Design for testability ECE 269 Krish Chakrabarty 2 1 International Technology Roadmap for Semiconductors http public itrs net Files 2003ITRS Home2003 htm 2005 updated document now available Manufacturing cost Test cost Krish Chakrabarty ECE 269 3 VLSI Realization Process Customer s need Determine requirements Write specifications Design synthesis and Verification Test development Fabrication Manufacturing test Chips to customer ECE 269 Krish Chakrabarty 4 2 Definitions Design synthesis Given an I O function develop a procedure to manufacture a device using known materials and processes Verification Predictive analysis to ensure that the synthesized design when manufactured will perform the given I O function Test A manufacturing step that ensures that the physical device manufactured from the synthesized design has no manufacturing defect Krish Chakrabarty ECE 269 5 Verification vs Test Verifies correctness of design Performed by simulation hardware emulation or formal methods Performed once prior to manufacturing Responsible for quality of design ECE 269 Verifies correctness of manufactured hardware Two part process 1 Test generation software process executed once during design 2 Test application electrical tests applied to hardware Test application performed on every manufactured device Responsible for quality of devices Krish Chakrabarty 6 3 Problems of Ideal Tests Ideal tests detect all defects produced in the manufacturing process Ideal tests pass all functionally good devices Very large numbers and varieties of possible defects need to be tested Difficult to generate tests for some real defects Defect oriented testing is an open problem ECE 269 Krish Chakrabarty 7 Real Tests Based on analyzable fault models which may not map on real defects Incomplete coverage of modeled faults due to high complexity Some good chips are rejected The fraction or percentage of such chips is called the yield loss Some bad chips pass tests The fraction or percentage of bad chips among all passing chips is called the defect level ECE 269 Krish Chakrabarty 8 4 Testing as a Filter Process Good chips Prob good y Prob pass test high Fabricated chips Pr Pr ob fa w il lo t t e tes st low ss pa ob Defective chips Prob bad 1 y Prob fail test high Krish Chakrabarty ECE 269 Mostly good chips Mostly bad chips 9 Costs of Testing Design for testability DFT Chip area overhead and yield reduction Performance overhead Software processes of test Test generation and fault simulation Test programming and debugging Manufacturing test Automatic test equipment ATE capital cost Test center operational cost ECE 269 Krish Chakrabarty 10 5 Design for Testability DFT DFT refers to hardware design styles or added hardware that reduces test generation complexity Motivation Test generation complexity increases exponentially with the size of the circuit Example Test hardware applies tests to blocks A and B and to internal bus avoids test generation for combined A and B blocks Int Logic Logic bus PI block A block B Test input ECE 269 PO Test output Krish Chakrabarty 11 Present and Future 1997 2001 2003 2006 Feature size micron 0 25 0 15 0 13 0 10 Transistors sq cm Pin count Clock rate MHz Power Watts 4 10M 18 39M 100 900 160 1475 200 730 530 1100 1 2 61 2 96 SIA Roadmap IEEE Spectrum July 1999 ECE 269 Krish Chakrabarty 12 6 Cost of Manufacturing Testing in 2000 0 5 1 0GHz analog instruments 1 024 digital pins ATE purchase price 1 2M 1 024 x 3 000 4 272M Running cost five year linear depreciation Depreciation Maintenance Operation 0 854M 0 085M 0 5M 1 439M year Test cost 24 hour ATE operation 1 439M 365 x 24 x 3 600 4 5 cents second ECE 269 Krish Chakrabarty 13 Automatic Test Equipment Agilent 93000 series ECE 269 Krish Chakrabarty 14 7 Roles of Testing Detection Determination whether or not the device under test DUT has some fault Diagnosis Identification of a specific fault that is present on DUT Device characterization Determination and correction of errors in design and or test procedure Failure mode analysis FMA Determination of manufacturing process errors that may have caused defects on the DUT Krish Chakrabarty ECE 269 15 A Modern VLSI Device System on a chip SOC Data terminal DSP core RAM ROM Interface logic Mixedsignal Codec Transmission medium Figure 18 5 page 605 ECE 269 Krish Chakrabarty 16 8 Course Outline Part I Introduction Basic concepts and definitions Chapter 1 Test process and ATE Chapter 2 Test economics and product quality Chapter 3 Fault modeling Chapter 4 ECE 269 Krish Chakrabarty 17 Course Outline Cont Part II Test Methods Logic and fault simulation Chapter 5 Testability measures Chapter 6 Combinational circuit ATPG Chapter 7 Sequential circuit ATPG Chapter 8 Memory test Chapter 9 Analog test Chapters 10 and 11 Delay test and IDDQ test Chapters 12 and 13 ECE 269 Krish Chakrabarty 18 9 Course Outline Cont Part III DFT Scan design Chapter 14 BIST Chapter 15 Boundary scan and analog test bus Chapters 16 and 17 System test and core based design Chapter 18 ECE 269 Krish Chakrabarty 19 Some Data from the ITRS 2003 Document Test and Test Equipment Potential Solutions ECE 269 Krish Chakrabarty 20 10 ITRS 2003 Data ECE 269 Krish Chakrabarty 21 ITRS 2003 Data ECE 269 Krish Chakrabarty 22 11 ITRS 2003 Data ECE 269 Krish Chakrabarty 23 ITRS 2003 Data ECE 269 Krish Chakrabarty 24 12 ITRS 2003 Data ECE 269 Krish Chakrabarty 25 13