1ECE 269Krish Chakrabarty1ECE 269VLSI System TestingKrish ChakrabartyLecture 1:OverviewECE 269Krish Chakrabarty2Lecture 1Introduction• VLSI realization process• Verification and test• Ideal and real tests• Costs of testing• Roles of testing• A modern VLSI device - system-on-a-chip• Course outline– Part I: Introduction to testing– Part II: Test methods– Part III: Design for testability2ECE 269Krish Chakrabarty3International Technology Roadmap for Semiconductorshttp://public.itrs.net/Files/2003ITRS/Home2003.htm(2005 updated document now available)Test costManufacturingcostECE 269Krish Chakrabarty4VLSI Realization ProcessDetermine requirementsWrite specificationsDesign synthesis and VerificationFabricationManufacturing testChips to customerCustomer’s needTest development3ECE 269Krish Chakrabarty5Definitions• Design synthesis: Given an I/O function, develop a procedure to manufacture a device using known materials and processes.• Verification: Predictive analysis to ensure that the synthesized design, when manufactured, will perform the given I/O function.• Test: A manufacturing step that ensures that the physical device, manufactured from the synthesized design, has no manufacturing defect.ECE 269Krish Chakrabarty6Verification vs. Test • Verifies correctness of design.• Performed by simulation, hardware emulation, or formal methods.• Performed once prior to manufacturing.• Responsible for quality of design.• Verifies correctness of manufactured hardware.• Two-part process:– 1. Test generation: software process executed once during design– 2. Test application: electrical tests applied to hardware• Test application performed on every manufactured device.• Responsible for quality of devices.4ECE 269Krish Chakrabarty7Problems of Ideal Tests• Ideal tests detect all defects produced in the manufacturing process.• Ideal tests pass all functionally good devices.• Very large numbers and varieties of possible defects need to be tested.• Difficult to generate tests for some real defects. Defect-oriented testing is an open problem.ECE 269Krish Chakrabarty8Real Tests• Based on analyzable fault models, which may not map on real defects.• Incomplete coverage of modeled faults due to high complexity.• Some good chips are rejected. The fraction (or percentage) of such chips is called the yield loss.• Some bad chips pass tests. The fraction (or percentage) of bad chips among all passing chips is called the defect level.5ECE 269Krish Chakrabarty9Testing as a Filter ProcessFabricatedchipsGood chipsDefective chipsProb(good) = yProb(bad) = 1- yProb(pass test) = highProb(fail test) = highProb(failtest) = lowProb(passtest) = lowMostlygoodchipsMostlybadchipsECE 269Krish Chakrabarty10Costs of Testing• Design for testability (DFT)– Chip area overhead and yield reduction– Performance overhead• Software processes of test– Test generation and fault simulation– Test programming and debugging• Manufacturing test– Automatic test equipment (ATE) capital cost– Test center operational cost6ECE 269Krish Chakrabarty11Design for Testability (DFT)DFT refers to hardware design styles or addedhardware that reduces test generation complexity.Motivation: Test generation complexity increasesexponentially with the size of the circuit.Logicblock ALogicblock BPIPOTestinputTestoutputInt.busExample: Test hardware applies tests to blocks Aand B and to internal bus; avoids test generationfor combined A and B blocks.ECE 269Krish Chakrabarty12Present and Future*Transistors/sq. cm 4 - 10M 18 - 39MPin count 100 - 900 160 - 1475Clock rate (MHz) 200 - 730 530 - 1100Power (Watts) 1.2 - 61 2 - 96Feature size (micron) 0.25 - 0.15 0.13 - 0.101997 -2001 2003 - 2006* SIA Roadmap, IEEE Spectrum, July 19997ECE 269Krish Chakrabarty13Cost of Manufacturing Testing in 2000• 0.5-1.0GHz, analog instruments,1,024 digital pins: ATE purchase price– = $1.2M + 1,024 x $3,000 = $4.272M• Running cost (five-year linear depreciation)–= Depreciation + Maintenance + Operation– = $0.854M + $0.085M + $0.5M– = $1.439M/year• Test cost (24 hour ATE operation)– = $1.439M/(365 x 24 x 3,600)– = 4.5 cents/secondECE 269Krish Chakrabarty14Automatic Test EquipmentAgilent 93000 series8ECE 269Krish Chakrabarty15Roles of Testing• Detection: Determination whether or not the device under test (DUT) has some fault.• Diagnosis: Identification of a specific fault that is present on DUT.• Device characterization: Determination and correction of errors in design and/or test procedure.• Failure mode analysis (FMA): Determination of manufacturing process errors that may have caused defects on the DUT.ECE 269Krish Chakrabarty16A Modern VLSI DeviceSystem-on-a-chip (SOC)DSPcoreRAMROMInter-facelogicMixed-signalCodecDataterminalTransmissionmediumFigure 18.5 (page 605)9ECE 269Krish Chakrabarty17Course OutlinePart I: Introduction• Basic concepts and definitions (Chapter 1)• Test process and ATE (Chapter 2)• Test economics and product quality (Chapter 3)• Fault modeling (Chapter 4)ECE 269Krish Chakrabarty18Course Outline (Cont.)Part II: Test Methods• Logic and fault simulation (Chapter 5)• Testability measures (Chapter 6)• Combinational circuit ATPG (Chapter 7)• Sequential circuit ATPG (Chapter 8)• Memory test (Chapter 9)• Analog test (Chapters 10 and 11)• Delay test and IDDQ test (Chapters 12 and 13)10ECE 269Krish Chakrabarty19Course Outline (Cont.)Part III: DFT• Scan design (Chapter 14)• BIST (Chapter 15)• Boundary scan and analog test bus (Chapters 16 and 17)• System test and core-based design (Chapter 18)ECE 269Krish Chakrabarty20Some Data from the ITRS 2003 DocumentTest and Test Equipment Potential Solutions11ECE 269Krish Chakrabarty21ITRS 2003 DataECE 269Krish Chakrabarty22ITRS 2003 Data12ECE 269Krish Chakrabarty23ITRS 2003 DataECE 269Krish Chakrabarty24ITRS 2003 Data13ECE 269Krish Chakrabarty25ITRS 2003