1ECE 269Krish Chakrabarty1ECE 269VLSI System TestingKrish ChakrabartyLecture 11:Sequential Circuit ATPG-1ECE 269Krish Chakrabarty2Sequential Circuits• A sequential circuit has memory in addition to combinational logic.• Test for a fault in a sequential circuit is a sequence of vectors, which• Initializes the circuit to a known state• Activates the fault, and• Propagates the fault effect to a primary output• Methods of sequential circuit ATPG• Time-frame expansion methods• Simulation-based methods2ECE 269Krish Chakrabarty3Testing Sequential Circuits• Difficult problem-internal states cannot be directly controlled and observed• Long test sequences are necessaryCombinationallogicRegistersPrimaryinputsPrimaryoutputs(controllable)(observable)State outputs(not observable)State inputs(not controllable)ECE 269Krish Chakrabarty4TaxonomySequential ATPGSynchronous AsynchronousState-table gate-level RTL-level + simulation- topologicalBased gate-level based analysis basedTopological Simulation- Hybridanalysis based based Known Unknowninitial state initial state3ECE 269Krish Chakrabarty5Fault Classification• Modes of operation– Synchronization mode: operation starts with specified synchronizing sequence– Free mode: no synchronization is done• Test generation approaches– Single observation time (SOT)– Multiple observation time (MOT)ECE 269Krish Chakrabarty6Single Observation Time• Definition: A fault f is detectable if there exists an input sequence I such that for every pair of initial states S and Sfof the fault-free and faulty circuits, respectively, the response z(I,S) of the fault-free circuit is different from the response z(I,Sf) of the faulty circuit at a specifiedtime unit j.• Motivation: Observe test responses at certain time units only, simpler testing strategy4ECE 269Krish Chakrabarty7Multiple Observation Time• Definition: A fault f is detectable if there exists an input sequence I such that for every pair of initial states S and Sfof the fault-free and faulty circuits, respectively, the response z(I,S) of the fault-free circuit is different from the response z(I,Sf) of the faulty circuit at sometime unit j.• Every fault detected under SOT is also detectable under MOT, reverse not true• MOT detects more faults (shorter test lengths) but difficult to implementECE 269Krish Chakrabarty8SOT vs MOTFF01MUXaczstuck-at-0Initial state unknownSOT approach:no test exists, faultundetectableMOT approach:• Fault detected by inputsequence (a,c) = {(1,1),(0,1)}Fault-free output sequence: {1,0}Faulty output (initial state = 0): {0,0}Faulty output (initial state = 1): {1,1}Fault detected (need to observe for both time steps)!5ECE 269Krish Chakrabarty9Partial Detection• Definition: A fault is redundant under given operation mode (synchronization or free) if, under all possible input sequences, it does not affect the output sequences.•A partial test is an input sequence I such that for at least one initial state Sfof the faulty circuit, zf(I,Sf) is different from the fault-free response z(I,S) for every fault-free initial state S.•A partial detectable fault has at least one partial test ⇒ redundant iff not partially detectableECE 269Krish Chakrabarty10Examplex1y1x1Y2zy2Y1s-a-1• Fault-free circuit initialized to (y1,y2) = (0,0) by sequence x1= {0,1,1}• Faulty circuit cannot be initializedState (1,1) disconnected from other statesin faulty machine• Fault-free response to x1= {0,1,1,0} isz = {X,X,X,0}• Faulty response for initial state (1,1) is{1,1,1,1} hence fault is detected for this case• Faulty response for any of the three otherinitial states is {X,X,X,0} hence fault is notdetected for these cases ⇒ partially detected6ECE 269Krish Chakrabarty11Fault Collapsing• Fault dominance for sequential circuits is more complex than for combinational circuit• Self-hiding effectx1Y1zy1x2x3c1c2• Fault c1/1 dominates x2/0 in combinationalportion, not for sequential circuit•(x1,x2,x3) = {(1,1,1), (1,1,0), (0,0,0)} detectsx2/0 but not c1/1• Fault effect propagated back and preventsfurther propagation of the fault!• c-equivalence and c-dominance vs s-equivalence and s-dominanceFFECE 269Krish Chakrabarty12Delayed Reconvergencex1Y1zy1x2x3c1c2FF• Faulty signals originating fromc-dominant and c-dominated faultsof a gate, passing through memory elements reconverge at gates with differentinversion paritiesExample: G1 has two propagation paths toG2 (different inversion polarities), G1 is a delayed reconvergence gate•c1/1 c-dominates x1/0, no s-dominance{(1,1,0),(1,0,0),(1,1,1)} detects x1/0but not c1/1 G1G27ECE 269Krish Chakrabarty13Fault Collapsing• A gate is non-SD iff it is both non-self-hiding and non-delayed-reconvergent• Use dominant fault collapsing for all non-SD gates• c-equivalence implies s-equivalence• Other collapsing methods:– Fanout branch is prime iff all propagation paths from other fanout branches of its fanout stem to PO pass through this branch – Faults at a prime fanout branch and its fanout stem are equivalentECE 269Krish Chakrabarty14Fault Collapsingx1Y1zy1x2x3c1c2FFG1G2• c2 is prime• Faults on c1 and c2 are equivalent• Non-delayed-reconvergent D flip-flop• No self-hiding possible (only one input)• Hence non-SD• Output SSL faults of a non-SD flip-flopdominate corresponding input SSL faults8ECE 269Krish Chakrabarty15Fault Collapsing• 8 lines, hence 16 possible SSL faults• G1, G2 and flip-flop are non-SD, c2is a prime fanout branchx1Y1zy1x2x3c1c2•Remove x1/1, x2/1, x3/1, z/1, c1/0 through equivalentfault collapsing• Remove c1/0 and z/0 through dominance• Remove c2/0 and c2/0 through prime fanout branchanalysis• Flip-flop is non-SD, so remove y1/0 and y1/1 • Only 5 SSL faults remain!FFG1G2Caveat: Irredeundant circuits: irredundant faults may get collapsedto redundant ones.ECE 269Krish Chakrabarty16Iterative Logic Array (ILA) Modelx1x2. . .xnx1x2. . .xnTimeframe 1Timeframe 2. . .z1z2zt. . .z1z2zty1y2ymY1Y2Ymy1y2ymSSL fault must be treated as a “multiple fault”, present in every time framex1x2. . .xnTimeframe N. . .z1z2zty1y2ym...9ECE 269Krish Chakrabarty17Fault Simulation Background• Fanout-free region FFR• If all paths from line p to primary outputs and next-state lines go through line q, then q is a dominator of p• No other dominator between a signal and its dominator ⇒immediate