ECE 269 VLSI System Testing Krish Chakrabarty Lecture 11 Sequential Circuit ATPG 1 ECE 269 Krish Chakrabarty 1 Sequential Circuits A sequential circuit has memory in addition to combinational logic Test for a fault in a sequential circuit is a sequence of vectors which Initializes the circuit to a known state Activates the fault and Propagates the fault effect to a primary output Methods of sequential circuit ATPG Time frame expansion methods Simulation based methods ECE 269 Krish Chakrabarty 2 1 Testing Sequential Circuits Difficult problem internal states cannot be directly controlled and observed Long test sequences are necessary Primary inputs controllable Primary outputs observable Combinational logic State inputs not controllable State outputs not observable Registers Krish Chakrabarty ECE 269 3 Taxonomy Sequential ATPG Synchronous State table Based Topological analysis based Asynchronous gate level RTL level gate level simulationbased topological analysis based Simulation Hybrid based Known Unknown initial state initial state ECE 269 Krish Chakrabarty 4 2 Fault Classification Modes of operation Synchronization mode operation starts with specified synchronizing sequence Free mode no synchronization is done Test generation approaches Single observation time SOT Multiple observation time MOT ECE 269 Krish Chakrabarty 5 Single Observation Time Definition A fault f is detectable if there exists an input sequence I such that for every pair of initial states S and Sf of the fault free and faulty circuits respectively the response z I S of the fault free circuit is different from the response z I Sf of the faulty circuit at a specified time unit j Motivation Observe test responses at certain time units only simpler testing strategy ECE 269 Krish Chakrabarty 6 3 Multiple Observation Time Definition A fault f is detectable if there exists an input sequence I such that for every pair of initial states S and Sf of the fault free and faulty circuits respectively the response z I S of the fault free circuit is different from the response z I Sf of the faulty circuit at some time unit j Every fault detected under SOT is also detectable under MOT reverse not true MOT detects more faults shorter test lengths but difficult to implement Krish Chakrabarty ECE 269 7 SOT vs MOT Initial state unknown 0 MUX a ECE 269 z 1 c SOT approach no test exists fault undetectable FF stuck at 0 MOT approach Fault detected by input sequence a c 1 1 0 1 Fault free output sequence 1 0 Faulty output initial state 0 0 0 Faulty output initial state 1 1 1 Fault detected need to observe for both time steps Krish Chakrabarty 8 4 Partial Detection Definition A fault is redundant under given operation mode synchronization or free if under all possible input sequences it does not affect the output sequences A partial test is an input sequence I such that for at least one initial state Sf of the faulty circuit zf I Sf is different from the fault free response z I S for every fault free initial state S A partial detectable fault has at least one partial test redundant iff not partially detectable Krish Chakrabarty ECE 269 9 Example z s a 1 x1 x1 y1 Y1 y2 ECE 269 Y2 Fault free circuit initialized to y1 y2 0 0 by sequence x1 0 1 1 Faulty circuit cannot be initialized State 1 1 disconnected from other states in faulty machine Fault free response to x1 0 1 1 0 is z X X X 0 Faulty response for initial state 1 1 is 1 1 1 1 hence fault is detected for this case Faulty response for any of the three other initial states is X X X 0 hence fault is not detected for these cases partially detected Krish Chakrabarty 10 5 Fault Collapsing Fault dominance for sequential circuits is more complex than for combinational circuit Self hiding effect Fault c1 1 dominates x2 0 in combinational portion not for sequential circuit z x1 x2 x3 1 1 1 1 1 0 0 0 0 detects x2 0 but not c1 1 Fault effect propagated back and prevents further propagation of the fault c equivalence and c dominance vs s equivalence and s dominance x1 c2 x2 x3 c1 y1 Y1 FF Krish Chakrabarty ECE 269 11 Delayed Reconvergence G2 G1 x1 x2 c2 c1 x3 y1 FF Y1 Faulty signals originating from c dominant and c dominated faults z of a gate passing through memory elements reconverge at gates with different inversion parities Example G1 has two propagation paths to G2 different inversion polarities G1 is a delayed reconvergence gate c1 1 c dominates x1 0 no s dominance 1 1 0 1 0 0 1 1 1 detects x1 0 but not c1 1 ECE 269 Krish Chakrabarty 12 6 Fault Collapsing A gate is non SD iff it is both non self hiding and non delayed reconvergent Use dominant fault collapsing for all non SD gates c equivalence implies s equivalence Other collapsing methods Fanout branch is prime iff all propagation paths from other fanout branches of its fanout stem to PO pass through this branch Faults at a prime fanout branch and its fanout stem are equivalent Krish Chakrabarty ECE 269 13 Fault Collapsing G2 G1 x1 x2 c2 c1 x3 y1 ECE 269 FF Y1 z c2 is prime Faults on c1 and c2 are equivalent Non delayed reconvergent D flip flop No self hiding possible only one input Hence non SD Output SSL faults of a non SD flip flop dominate corresponding input SSL faults Krish Chakrabarty 14 7 Fault Collapsing 8 lines hence 16 possible SSL faults G1 G2 and flip flop are non SD c2 is a prime fanout branch Remove x1 1 x2 1 x3 1 z 1 c1 0 through equivalent G2 x1 G1 x2 x3 c2 z c1 y1 FF Y1 fault collapsing Remove c1 0 and z 0 through dominance Remove c2 0 and c2 0 through prime fanout branch analysis Flip flop is non SD so remove y1 0 and y1 1 Only 5 SSL faults remain Caveat Irredeundant circuits irredundant faults may get collapsed to redundant ones Krish Chakrabarty ECE 269 15 Iterative Logic Array ILA Model y1 y2 x1 x2 xn Time frame 1 Y1 y1 Y2 y2 x1 x2 xn Time frame 2 Ym ym ym z1 z2 zt z1 z2 zt y1 y2 x1 x2 xn Time frame N ym z1 z2 zt SSL fault must be treated as a multiple fault present in every time frame ECE 269 Krish Chakrabarty 16 8 Fault Simulation Background Fanout free region FFR If all paths from line p to primary outputs and next state lines go through line q then q is a dominator of p No other dominator between a signal and its dominator immediate dominator FFR c1 y x2 FFR c5 x1 FFR Y Y c4 c1 c5 z x4 x3 FFR z c4 and c5 are dominators of c1 c4 is an immediate dominator c5 does not have a dominator Krish Chakrabarty ECE 269 17 Fault Classification Single event faults fault free and faulty values on present state lines are