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ECE 269VLSI System TestingKrish ChakrabartyDelay-Fault Testing: 2Acknowledgment: Mahmut Yilmaz2OutlineOutline• Motivation• Probabilistic Delay‐Fault Model and Output Deviations for Screening Small Delay Defects (SDDs)– Gate and Signal‐Transition Probability Definitions–Propagation of Signal‐Transition Probabilities–Output Deviations Based on Delay Differences• Pattern Selection and Re‐ordering•Path Length and Output Deviation Correlation Analysis• Simulation Results• Conclusions3Motivation: Decreasing feature sizesMotivation: Decreasing feature sizes……•Process technology scales down continuouslyVery Deep Submicron (VDSM) designsMotivation: Motivation: ……Increasing Defect RatesIncreasing Defect Rates4L=10% tOX=3% VTH=30%Resistive shorts, bridgesResistive opensMore effective crosstalkIncreased sensitivity to process variationsAll of them are sources of small delay defectsCcCc90nm45nmPictures from M. TehranipoorMotivation: Shortcomings of current Motivation: Shortcomings of current methodsmethods•Stuck at fault model–Not sufficient for high quality test•Traditional transition‐test ATPG does not target SDDs– Inclined to select short activation paths•The pattern generation methods usually use SCOPE measure–SDDsare observable on short‐slack paths (long paths)• Recently developed timing‐aware ATPG tools– Recent versions of Mentor Graphics FastScan, Cadence True Time ATPG, Synopsys TetraMax–Are they doing as good as expected? Real defect causes are covered?5 RI SDUWV$ GGLWL RQDO GHOD\Small delay defectsLarge delay defectsMotivation: Long ATPG RunMotivation: Long ATPG Run‐‐timetime• Industrial timing‐aware ATPG tools take very long time to generate transition‐test patterns–They usually perform path enumeration–This may be unacceptable due to time‐to‐market constraints6* Timing‐aware ATPG tool: Mentor Graphics FastScan 2007_2Probabilistic DelayProbabilistic Delay‐‐Fault Model and Fault Model and Output Deviations for Small Delay DefectsOutput Deviations for Small Delay Defects•Gate Delay Defect Probabilities (DDP)–The probability that the delay of a gate is larger than a delay limit–For each input transition, the gate has a different delay distribution–Set a critical delay limit for the gate: Dcrt– Dcrt: Relaxed limit, can be set to MAX delay reported by STA–DDP: The probability that the gate delay is more than Dcrt for the given input transition7DcrtDcrt11Æ 0100Æ 10DelayProbabilityProbabilistic DelayProbabilistic Delay‐‐Fault Model and Fault Model and Output Deviations for Small Delay DefectsOutput Deviations for Small Delay Defects•Delay Defect Probability Matrix (DDPM)–With DDP for all possible input transitions, we can form a matrix of DDPs: Delay Defect Probability Matrix–Example: DDPM for an OR2 gate (entries are arbitrary)8OR2 Initial Input State [IN0,IN1]Prob. (PL→H)(PH→L)00 01 10 11InputsIN0(0.2)(0) (0)(0) (0)(0.5) (0)(0.1)IN1(0.1)(0) (0)(0.2) (0)(0) (0)(0.1)At most one of the probabilities can be non‐zeroHÆLProbabilistic DelayProbabilistic Delay‐‐Fault Model and Fault Model and Output Deviations for Small Delay DefectsOutput Deviations for Small Delay Defects• Signal Transition Probabilities–Transition Delay Fault (TDF) test‐patterns will force signal transitionson circuit nets– Assuming that there are only two possible signal values (Low andHigh), each net may have one of the four different signal transitions:•Low Æ Low: Signal value stays at low•Low Æ High: Signal value changes from low to high•High Æ Low: Signal value changes from high to low•High Æ High: Signal value stays at high– Each of these events has a probability to occur– Each net has a vector of signal‐transition probabilities:•Net: <PLÆL , PLÆH , PHÆL , PHÆH>9Probabilistic DelayProbabilistic Delay‐‐Fault Model and Fault Model and Output Deviations for Small Delay DefectsOutput Deviations for Small Delay Defects•Propagation of Signal Transition Probabilities (STPs)–The nets connected to the test‐application points: Initialization nets (INs) Æ Initialized with “0” DDP–During signal propagation through circuit, use DDPM of the gates to update signal‐transition probabilities10The probability that net A will have the expected signal‐transition, PEXPECTEDDeviation: 1 ‐ PEXPECTEDProbabilistic DelayProbabilistic Delay‐‐Fault Model and Fault Model and Output Deviations for Small Delay DefectsOutput Deviations for Small Delay Defects•Rules of STP Propagation1) If output does not change, the deviation on output net is 0.2) If any one of the multiple input‐transitions can cause the output transition, only the maximum deviation provider is considered3) If multiple input‐transitions are required for an output transition, all required input‐transitions are considered•Deviation increase through a sensitized path Æ Proven11Probabilistic DelayProbabilistic Delay‐‐Fault Model and Fault Model and Output Deviations for Small Delay DefectsOutput Deviations for Small Delay Defects•An example (arbitrary DDPMs):12Initialization of signal transition probabilities on INsExpected signal transitions are shown in dark boxesProbabilistic DelayProbabilistic Delay‐‐Fault Model and Fault Model and Output Deviations for Small Delay DefectsOutput Deviations for Small Delay Defects•An example:13There is no transition on net E.The probability of a delay fault (deviation) is 0.Probabilistic DelayProbabilistic Delay‐‐Fault Model and Fault Model and Output Deviations for Small Delay DefectsOutput Deviations for Small Delay Defects•An example:14XOR2 Initial Input StateProb. (PL→H)(PH→L)00 01 10 11InputsIN0 (0.3)(0) (0)(0.4) (0)(0.2) (0.3)(0)IN1 (0.3)(0) (0)(0.4) (0)(0.1) (0.4)(0)The output changes due to IN1.Probability of a delay fault: 0.4Probabilistic DelayProbabilistic Delay‐‐Fault Model and Fault Model and Output Deviations for Small Delay DefectsOutput Deviations for Small Delay Defects•An example:–The output deviation (for each observable output) for an input pattern is the probability that the output value is different from the expected value.15Output Deviations:Q1: 0.52Q2: 0.664Probabilistic DelayProbabilistic Delay‐‐Fault Model and Fault Model and Output Deviations for Small Delay DefectsOutput Deviations for Small Delay Defects•An example:– Relative deviations at the observation points are considered• Absolute


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Duke ECE 269 - VLSI System Testing

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