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1ECE 269Krish Chakrabarty1ECE 269VLSI System TestingKrish ChakrabartyLecture 14:Design for Testability (DFT): 2ECE 269Krish Chakrabarty2Outline• Systematic DFT Methods• Scan Design– Scan cells– Scan chains• Boundary Scan2ECE 269Krish Chakrabarty3Scan Design• Make all flip-flops directly controllable and observable by adding multiplexers• Popular design-for-test (DFT) technique: circuit is now combinational for testing purposesCombinationallogicPrimaryinputsPrimaryoutputsScan inScan outScan cellsState inputsState outputs(controllable)(observable)ECE 269Krish Chakrabarty4Scan Design– Circuit is designed using pre-specified design rules.– Test structure (hardware) is added to the verified design:•Add a test control (TC) primary input.• Replace flip-flops by scan flip-flops (SFF) and connect to form one or more shift registers in the test mode.• Make input/output of each scan shift register controllable/observable from PI/PO.– Use combinational ATPG to obtain tests for all testable faults in the combinational logic.– Add shift register tests and convert ATPG tests into scan sequences for use in manufacturing test.3ECE 269Krish Chakrabarty5Scan DesignConcept• Memory elements (latches and flip-flops) are designed so thatthey can be reconfigured dynamically to form a shift register Rduring testing• Test data transferred serially to and from R making memory state completely controllable and observableCombinationalcircuitCombinationalcircuitNormal operating modeTest modeECE 269Krish Chakrabarty6Scan Cell Design01DQScan in(Test data)Data(Functional)N/TN/T = 1: Test modeN/T = 0: Normal modeQ3ClockScaninD0D1D2D3ScanoutN/TQ0Q1Q2Clock4ECE 269Krish Chakrabarty7Scan Design• Separate input and output 4-bit scan registers• Test sequence: {01100, 11011}, first 4 bits are for flip-flopsCombinational circuitCombinational circuitScan chain/Scan pathTest dataTest responses0110110110ControllableprimaryinputN/TN/TECE 269Krish Chakrabarty8Steps in Scan Testing• N/T = 1: Scan in test pattern, hold appropriate bit pattern on controllable primary inputs• N/T = 0: Apply test pattern to combinational circuit• N/T=1: Scan out test responses• Scan provides complete controllability and observability• Testing time? How many cycles? How to test scan registers?5ECE 269Krish Chakrabarty9Long Scan ChainsNormal dataTest vectors need to be translated to scan formatScan chainTest dataECE 269Krish Chakrabarty10Comments on Scan Design• Allows complete controllability and observability• Test pattern must be generated primarily for the combinational circuit• Hardware overhead is small: a few extra pins and some (5 to 20%) extra logic for the latches and flip-flops• Test application is slow• Limited to a few hundred latches6ECE 269Krish Chakrabarty11Scan Design Rules• Use only clocked D-type of flip-flops for all state variables.• At least one PI pin must be available for test; more pins, if available, can be used.• All clocks must be controlled from PIs.• Clocks must not feed data inputs of flip-flops.ECE 269Krish Chakrabarty12Correcting a Rule Violation• All clocks must be controlled from PIs.Comb.logicComb.logicD1D2CKQFFComb.logicD1D2CKQFFComb.logic7ECE 269Krish Chakrabarty13Scan TestingI2I1O1O2S2S1N2N1CombinationallogicPIPresentstatePONextstateSCANINTCSCANOUTECE 269Krish Chakrabarty14Scan TestingI2I1O1O2PIPOSCANINSCANOUTS1 S2 N1 N2 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0TCDon’t careor randombitsSequence length= (ncomb+ 1) nsff+ ncombclock periodsncomb= number of combinational vectorsnsff= number of scan flip-flops(nsff+ 1) ncomb+ nsffclock periods8ECE 269Krish Chakrabarty15Testing Scan Register• Scan register must be tested prior to application of scan test sequences.• A shift sequence 00110011 . . . of length nsff+4 in scan mode (TC=0) produces 00, 01, 11 and 10 transitions in all flip-flops and observes the result at SCANOUT output.• Total scan test length: (ncomb+ 2) nsff+ ncomb+ 4 clock periods.• Example: 2,000 scan flip-flops, 500 comb. vectors, total scan test length ~ 106clocks.• Multiple scan registers reduce test length.ECE 269Krish Chakrabarty16Multiple Scan Registers• Scan flip-flops can be distributed among any number of shift registers, each having a separate scanin and scanoutpin.• Test sequence length is determined by the longest scan shift register.• Just one test control (TC) pin is essential.SFFSFFSFFCombinationallogicPI/SCANINPO/SCANOUTMUXCKTC9ECE 269Krish Chakrabarty17Automated Scan DesignBehavior, RTL, and logicDesign and verificationGate-levelnetlistScan designrule auditsCombinationalATPGScan hardwareinsertionChip layout: Scan-chain optimization,timing verificationScan sequenceand test programgenerationDesign and testdata formanufacturingRuleviolationsScannetlistCombinationalvectorsScan chain orderMask dataTest programECE 269Krish Chakrabarty18Timing and Power• Small delays in scan path and clock skew can cause race condition.• Large delays in scan path require slower scan clock.• Dynamic multiplexers: Skew between TC and TC signals can cause momentary shorting of D and SD inputs.• Random signal activity in combinational circuit during scan can cause excessive power dissipation.10ECE 269Krish Chakrabarty19Summary• Scan is the most popular DFT technique:• Rule-based design• Automated DFT hardware insertion• Combinational ATPG• Advantages:• Design automation• High fault coverage; helpful in diagnosis• Hierarchical – scan-testable modules are easily combined into large scan-testable systems• Moderate area (~10%) and speed (~5%) overheads• Disadvantages:• Large test data volume and long test time• Basically a slow speed (DC) testECE 269Krish Chakrabarty20Boundary Scan• IEEE standard 1149.1 for incorporating scan design into chips and boards• Shift latch placed at each pin• Originally envisaged for PCBs, but also applicable to MCMs and core-based systems-on-a-chipLatchMuxSignalinSignaloutMuxShiftScan data outMode controlClockScan data in110011ECE 269Krish Chakrabarty21Boundary ScanPCB boardedge connectorSCAN INSCAN OUTScan chain(heavy lines)Boundary scan cellI/O


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