ECE 269 VLSI System Testing Krish Chakrabarty Lecture 14 Design for Testability DFT 2 ECE 269 Krish Chakrabarty 1 Outline Systematic DFT Methods Scan Design Scan cells Scan chains Boundary Scan ECE 269 Krish Chakrabarty 2 1 Scan Design Make all flip flops directly controllable and observable by adding multiplexers Popular design for test DFT technique circuit is now combinational for testing purposes Primary inputs Combinational logic Primary outputs Scan out State inputs controllable Scan cells State outputs observable Scan in ECE 269 Krish Chakrabarty 3 Scan Design Circuit is designed using pre specified design rules Test structure hardware is added to the verified design Add a test control TC primary input Replace flip flops by scan flip flops SFF and connect to form one or more shift registers in the test mode Make input output of each scan shift register controllable observable from PI PO Use combinational ATPG to obtain tests for all testable faults in the combinational logic Add shift register tests and convert ATPG tests into scan sequences for use in manufacturing test ECE 269 Krish Chakrabarty 4 2 Scan Design Concept Memory elements latches and flip flops are designed so that they can be reconfigured dynamically to form a shift register R during testing Test data transferred serially to and from R making memory state completely controllable and observable Combinational circuit Combinational circuit Test mode Normal operating mode Krish Chakrabarty ECE 269 5 Scan Cell Design Data 0 Functional D Scan in Test data 1 N T 0 Normal mode N T D0 N T 1 Test mode Q Clock D1 D2 D3 Scan out Scan in N T Clock ECE 269 Q0 Q1 Krish Chakrabarty Q2 Q3 6 3 Scan Design Separate input and output 4 bit scan registers Test sequence 01100 11011 first 4 bits are for flip flops 1 Controllable 0110 0 primary input 1101 Test data Scan chain Scan path N T Combinationalcircuit circuit Combinational Test responses N T ECE 269 Krish Chakrabarty 7 Steps in Scan Testing N T 1 Scan in test pattern hold appropriate bit pattern on controllable primary inputs N T 0 Apply test pattern to combinational circuit N T 1 Scan out test responses Scan provides complete controllability and observability Testing time How many cycles How to test scan registers ECE 269 Krish Chakrabarty 8 4 Normal data Long Scan Chains Test data ECE 269 Scan chain Test vectors need to be translated to scan format Krish Chakrabarty 9 Comments on Scan Design Allows complete controllability and observability Test pattern must be generated primarily for the combinational circuit Hardware overhead is small a few extra pins and some 5 to 20 extra logic for the latches and flip flops Test application is slow Limited to a few hundred latches ECE 269 Krish Chakrabarty 10 5 Scan Design Rules Use only clocked D type of flip flops for all state variables At least one PI pin must be available for test more pins if available can be used All clocks must be controlled from PIs Clocks must not feed data inputs of flip flops Krish Chakrabarty ECE 269 11 Correcting a Rule Violation All clocks must be controlled from PIs Comb logic D1 Q Comb logic FF D2 CK Comb logic D1 D2 ECE 269 CK Krish Chakrabarty Q FF Comb logic 12 6 Scan Testing PI I2 I1 O1 Combinational SCANIN TC Present state O2 SCANOUT logic N1 S2 S1 PO N2 Next state Krish Chakrabarty ECE 269 13 Scan Testing SCANIN I2 I1 PI S1 S2 TC 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 PO SCANOUT Don t care or random bits 1 0000000 O2 O1 N1 N2 nsff 1 ncomb nsff clock periods Sequence length ncomb 1 nsff ncomb clock periods ncomb number of combinational vectors nsff number of scan flip flops ECE 269 Krish Chakrabarty 14 7 Testing Scan Register Scan register must be tested prior to application of scan test sequences A shift sequence 00110011 of length nsff 4 in scan mode TC 0 produces 00 01 11 and 10 transitions in all flip flops and observes the result at SCANOUT output Total scan test length ncomb 2 nsff ncomb 4 clock periods Example 2 000 scan flip flops 500 comb vectors total scan test length 106 clocks Multiple scan registers reduce test length Krish Chakrabarty ECE 269 15 Multiple Scan Registers Scan flip flops can be distributed among any number of shift registers each having a separate scanin and scanout pin Test sequence length is determined by the longest scan shift register Just one test control TC pin is essential PI SCANIN Combinational logic SFF SFF M U X PO SCANOUT SFF TC CK ECE 269 Krish Chakrabarty 16 8 Automated Scan Design Behavior RTL and logic Design and verification Rule violations Scan design rule audits Gate level netlist Combinational ATPG Scan hardware insertion Scan netlist Combinational vectors Scan sequence and test program generation Test program ECE 269 Scan chain order Design and test data for manufacturing Chip layout Scanchain optimization timing verification Mask data Krish Chakrabarty 17 Timing and Power Small delays in scan path and clock skew can cause race condition Large delays in scan path require slower scan clock Dynamic multiplexers Skew between TC and TC signals can cause momentary shorting of D and SD inputs Random signal activity in combinational circuit during scan can cause excessive power dissipation ECE 269 Krish Chakrabarty 18 9 Summary Scan is the most popular DFT technique Rule based design Automated DFT hardware insertion Combinational ATPG Advantages Design automation High fault coverage helpful in diagnosis Hierarchical scan testable modules are easily combined into large scan testable systems Moderate area 10 and speed 5 overheads Disadvantages Large test data volume and long test time Basically a slow speed DC test Krish Chakrabarty ECE 269 19 Boundary Scan IEEE standard 1149 1 for incorporating scan design into chips and boards Shift latch placed at each pin Originally envisaged for PCBs but also applicable to MCMs and core based systems on a chip Scan data out Signal in Shift 0 Signal out Mux 1 Mux Latch 1 Mode control Clock ECE 269 0 Krish Chakrabarty Scan data in 20 10 Boundary Scan I O pin PCB board edge connector SCAN IN SCAN OUT Boundary scan cell ECE 269 Krish Chakrabarty Scan chain heavy lines 21 11