ECE 269 VLSI System Testing Krish Chakrabarty Lecture 19 Functional Testing ECE 269 Krish Chakrabarty 1 Outline Universal test sets Pseudo exhaustive testing Verification testing Hardware segmentation Sensitized segmentation ILA testing C testability Microprocessor testing ECE 269 Krish Chakrabarty 2 1 Universal Test Sets Implementation independent tests need to be exhaustive unless restrictions are placed on the structure All combinational faults detected not just stuck at etc i e detects any changes in truth table a b Circuit consisting only of AND and OR gates z c Inversions only on primary inputs use De Morgan s theorem ECE 269 Krish Chakrabarty 3 Some Definitions A vector X x1 x2 xn covers another vector Y y1 y2 yn if for all i yi 1 xi 1 A function z x1 x2 xn is positive negative unate in variable xi if for all x1 x2 xi 1 xi 1 xn z x1 xi 1 0 xi 1 xn is covered by covers z x1 xi 1 1 xi 1 xn Positive negative unate in xi implies xi appears only in uncomplemented complemented form in Boolean formula If function is neither positive unate or negative unate in xi then it is binate in xi Function is unate if it is positive or negative unate in all its variables otherwise binate ECE 269 Krish Chakrabarty 4 2 More Definitions True false vector makes function 1 0 Minimal true vector does not cover any true vector Maximal false vector is not covered by any false vector z x1x2 x2x3 x1 x2 x2 x3 z Minimal true Maximal false vector vector 0 0 1 0 0 0 0 1 1 1 0 1 0 0 0 0 1 0 1 0 1 0 1 0 0 1 0 1 1 1 1 1 0 0 1 1 1 0 1 1 Union of minimal true vectors and maximal false vectors is the universal test set Krish Chakrabarty ECE 269 5 Universal Test Sets Universal test sets can be applied to a Circuit b can be transformed to a using de Morgan s law Circuit c can be reduced to the restricted form x1 x2 x1 x2 z x2 x3 a ECE 269 z x2 x3 x1 x2 z x2 x3 b Krish Chakrabarty c 6 3 Pseudo exhaustive Testing Impractical to apply 2n vectors for large n Pseudo exhaustive testing test segments exhaustively Segments consist of logic with smaller number of inputs but not necessarily disjoint Techniques Verification testing Hardware segmentation Sensitized segmentation Krish Chakrabarty ECE 269 7 Verification Testing n inputs m outputs x1 x2 x3 x4 z1 x1 x2 x3 z2 x2 x3 x4 Partition columns of DM into different sets such that each row of a set has at most one 1 Number of sets p must be minimized x1 x2 x3 x4 z1 1 1 1 0 z2 0 1 1 1 Dependence Matrix DM ECE 269 x1 x4 x2 x3 z1 1 0 1 1 z2 0 1 1 1 Partitioned Dependence Matrix PDM Krish Chakrabarty 8 4 Verification Testing Reduced Partitioned Dependence Matrix RPDM Replace each row within each partition of PDM by the logical OR of the entries in it x1 x4 x2 x3 z1 1 1 1 z2 1 1 1 Reduced Partitioned Dependence Matrix RPDM m by p matrix One test signal input needed for each column of RPDM Test signal affects zi if there is 1 in corresponding row ECE 269 Krish Chakrabarty 9 Hardware Segmentation Verification testing not feasible for many circuits e g adders Circuit partitioning segmentation by inserting multiplexers Circuit segmented into k 1 possibly overlapping segments Si tested exhaustively Each segment Si has n Si ni pi inputs ni primary inputs and pi inputs from segmentation cuts Total testing time 2n Si 2ni pi Test time minimization problem is NP complete ECE 269 Krish Chakrabarty 10 5 Hardware Segmentation n1 S1 n1 n2 p2 S2 M U X S1 M U X p1 n2 n1 n2 p2 S2 p2 n1 n2 p2 S1 S2 S2 S1 p1 p1 Configuration to test S2 Configuration to test S1 Krish Chakrabarty ECE 269 11 Hardware Segmentation Example S1 x1 x2 x3 z1 S2 x4 x5 z2 Insert multiplexer ECE 269 Krish Chakrabarty 12 6 Sensitized Segmentation Test each segment by sensitizing paths from primary inputs to segment inputs and from segment output to primary outputs Exhaustive testing of the segments is not guaranteed E g To test S1 all combinations of x2 and x3 and x1 x4 1 x5 0 To test S2 all combinations of inputs at AND gate and observe z1 S2 x1 S x2 1 x3 x4 x5 ECE 269 z1 S3 S4 z2 Krish Chakrabarty 13 Testing Regular Circuits Definition Array like circuits composed of nearly identical subcircuits or cells with nearly uniform interconnections Can generally be tested with O n tests sometimes less Examples Random access memories RAMs and ROMs Bit sliced processors Arithmetic circuits adders multipliers etc Iterative Logic Arrays ECE 269 Krish Chakrabarty 14 7 C Testability Ripple carry adder All cell faults in an N bit adder can be detected by 8 test patterns for any N it is C testable 0 0 0 0 0 0 0 0 FA FA FA FA 1 0 1 0 1 0 1 0 FA FA FA FA 0 0 0 1 0 1 0 1 0 1 FA FA FA FA 0 0 1 1 0 0 1 1 FA FA FA FA Krish Chakrabarty ECE 269 0 0 15 C Tests for Ripple Carry Adder 1 1 0 0 1 1 0 0 FA FA FA FA 1 0 1 0 1 0 1 0 FA FA FA FA ECE 269 1 1 0 1 0 1 0 1 0 1 FA FA FA FA 1 1 1 1 1 1 1 1 FA FA FA FA Krish Chakrabarty 1 1 16 8 C Testability Other C testable ILAs include simple bit sliced ALUs multipliers and dividers Theorem A one dimensional ILA is C testable iff its equivalent sequential circuit has a reduced state table flow table and for every transition from state Y there exists a sequence that returns it to Y 00 0 01 0 01 1 11 0 0 10 1 00 1 1 10 0 11 1 A non C testable ILA can be made testable by modifying the cell s behavior to satisfy the above theorem Krish Chakrabarty ECE 269 17 Application of Functional Testing Typical problem Testing a microprocessor on chip CPU or a microprocessor based system microcontroller Features Goal Check system for correct operation with respect to functional specifications High complexity may preclude explicit fault model Methods are often heuristic or ad hoc Parts of the system are often tested exhaustively ECE 269 Krish Chakrabarty 18 9 Microprocessor Testing CPU microprocessor Data Control Address ATE Instruction cycle 1 PC increments and outputs its instruction address A 2 M responds with instruction word I M A 3 CPU executes I Instruction set serves a test set Test program ECE 269 Krish Chakrabarty 19 Microprocessor Testing Reset the microprocessor Test the program counter by enabling it through all its states via the NOP …