ECE 269 VLSI System Testing Krish Chakrabarty Lecture 2 Test Process and Equipment Krish Chakrabarty ECE 269 1 Lecture 2 VLSI Testing Process and Equipment ECE 269 Motivation Types of Testing Test Specifications and Plan Test Programming Test Data Analysis Automatic Test Equipment Parametric Testing Summary Krish Chakrabarty 2 1 Motivation Need to understand some Automatic Test Equipment ATE technology Influences what tests are possible Serious analog measurement limitations at high digital frequency or in the analog domain Need to understand capabilities for digital logic memory and analog test in System on a Chip SOC technology Need to understand parametric testing Used to take setup hold time measurements Use to compute VIL VIH VOL VOH tr tf td IOL IOH IIL IIH ECE 269 Krish Chakrabarty 3 Types of Testing Verification testing characterization testing or design debug Verifies correctness of design and of test procedure usually requires correction to design Manufacturing testing Factory testing of all manufactured chips for parametric faults and for random defects Acceptance testing incoming inspection User customer tests purchased parts to ensure quality ECE 269 Krish Chakrabarty 4 2 Testing Principle ECE 269 Krish Chakrabarty 5 Automatic Test Equipment Components Consists of Powerful computer Powerful 32 bit Digital Signal Processor DSP for analog testing Test Program written in high level language running on the computer Probe Head actually touches the bare or packaged chip to perform fault detection experiments Probe Card or Membrane Probe contains electronics to measure signals on chip pin or pad ECE 269 Krish Chakrabarty 6 3 Characterization Test Worst case test Choose test that passes fails chips Select statistically significant sample of chips Repeat test for every combination of 2 environmental variables Plot results in Schmoo plot Diagnose and correct design errors Continue throughout production life of chips to improve design and process to increase yield ECE 269 Krish Chakrabarty 7 Schmoo Plot ECE 269 Krish Chakrabarty 8 4 Manufacturing Test Determines whether manufactured chip meets specs Must cover high of modeled faults Must minimize test time to control cost No fault diagnosis Tests every device on chip Test at speed of application or speed guaranteed by supplier Krish Chakrabarty ECE 269 9 Burn in or Stress Test Process Subject chips to high temperature over voltage supply while running production tests Catches Infant mortality cases these are damaged chips that will fail in the first few days of operation causes bad devices to actually fail before chips are shipped to customers Freak failures ECE 269 Krish Chakrabarty 10 5 Types of Manufacturing Tests Wafer sort or probe test done before wafer is scribed and cut into chips Includes test site characterization specific test devices are checked with specific patterns to measure Gate threshold Polysilicon field threshold Poly sheet resistance etc Packaged device tests ECE 269 Krish Chakrabarty 11 Sub types of Tests Parametric measures electrical properties of pin electronics delay voltages currents etc fast and cheap Functional used to cover very high of modeled faults test every transistor and wire in digital circuits long and expensive ECE 269 Krish Chakrabarty 12 6 Two Different Meanings of Functional Test ATE and Manufacturing World any vectors applied to cover high of faults during manufacturing test Automatic Test Pattern Generation World testing with verification vectors which determine whether hardware matches its specification typically have low fault coverage 70 ECE 269 Krish Chakrabarty 13 Test Specifications Plan Test Specifications Functional Characteristics Type of Device Under Test DUT Physical Constraints Package pin numbers etc Environmental Characteristics supply temperature humidity etc Reliability acceptance quality level defects million failure rate etc Test plan generated from specifications Type of test equipment to use Types of tests Fault coverage requirement ECE 269 Krish Chakrabarty 14 7 Test Programming ECE 269 Krish Chakrabarty 15 Test Data Analysis Uses of ATE test data Reject bad DUTs Fabrication process information Design weakness information Devices that did not fail are good only if tests covered 100 of faults Failure mode analysis FMA Diagnose reasons for device failure and find design and process weaknesses Allows improvement of logic layout design rules ECE 269 Krish Chakrabarty 16 8 ADVANTEST Model T6682 ATE ECE 269 Krish Chakrabarty 17 LTX FUSION HF ATE ECE 269 Krish Chakrabarty 26 9 Multi site Testing Major Cost Reduction One ATE tests several usually identical devices at the same time For both probe and package test DUT interface board has 1 socket Add more instruments to ATE to handle multiple devices simultaneously Usually test 2 or 4 DUTS at a time usually test 32 or 64 memory chips at a time Limits instruments available in ATE type of handling equipment available for package Krish Chakrabarty ECE 269 28 Wrap Up Parametric tests determine whether pin electronics system meets digital logic voltage current and delay time specs Functional tests determine whether internal logic analog sub systems behave correctly ATE Cost Problems Pin inductance expensive probing Multi GHz frequencies High pin count 1024 ATE Cost Reduction Multi Site Testing DFT methods like Built In Self Test ECE 269 Krish Chakrabarty 33 10 Economics of Design for Testability DFT Consider life cycle cost DFT on chip may impact the costs at board and system levels Weigh costs against benefits Cost examples reduced yield due to area overhead yield loss due to non functional tests Benefit examples Reduced ATE cost due to selftest inexpensive alternatives to burn in test Krish Chakrabarty ECE 269 34 Benefits and Costs of DFT Level Design and test Fabrication Manuf Test Chips Boards System Maintenance test Diagnosis and repair Service interruption Cost increase Cost saving Cost increase may balance cost reduction ECE 269 Krish Chakrabarty 35 11 Summary Economics teaches us how to make the right trade offs It combines common sense experience and mathematical methods The overall benefit cost ratio for design test and manufacturing should be maximized one should select the most economic design over the cheapest design A DFT or test method should be selected to improve the product quality with minimal increase in cost due to area overhead and yield loss ECE 269 Krish Chakrabarty 36 12