ECE 269 VLSI System Testing Krish Chakrabarty Built In Self Test BIST Krish Chakrabarty ECE 269 1 Taxonomy BIST methods Off line Functional ECE 269 Structural On line Concurrent Krish Chakrabarty Non concurrent 2 1 Test Per Scan BIST ScanBIST LFSR Pattern generator Scan chain Circuit under test LFSR Response monitor High testing time one pattern every n 1 cycles At speed testing not possible Low performance degradation none beyond scan Fairy low overhead Krish Chakrabarty ECE 269 3 Test Per Clock BIST Input scan register reconfigured as TPG Circuit under test Output scan register reconfigured as SA Suitable for register based designs Low testing time one pattern every cycle At speed testing achieved Performance degradation delay on functional paths Overhead may be high ECE 269 Krish Chakrabarty 4 2 BIST Pattern Generators LFSRs are good pseudorandom pattern generators Low cost easy to implement Suitable for test per scan and test per clock LFSR generated patterns exhibit high degree of randomness can be measured through statistical correlation tests ECE 269 Krish Chakrabarty 5 BIST Pattern Generators For test per clock BIST non random patterns are often needed especially for random pattern resistant faults Test length with pseudorandom patterns only is excessive How to generate non random patterns Use weighted random patterns Use mapping logic LFSR LFSR Mapping logic ECE 269 Krish Chakrabarty 6 3 BIST Pattern Generators For scan BIST the bits in the LFSR sequence should have low linear correlation and sequence length should be large Use primitive polynomials Use longer LFSRs Use bit fixing logic Scan chain LFSR Bit fixing logic Scan chain LFSR From LFSR Fix 0 Fix 1 From control logic Krish Chakrabarty ECE 269 Test patterns 7 BIST Architectures CUT CUT Distribution circuit TPG Distribution circuit Chip SA Centralized and separate BIST Lower overhead Lower fault coverage and high testing time Easy to control and implement BIST controller ECE 269 Krish Chakrabarty 8 4 BIST Architectures Chip TPG TPG CUT CUT Distributed and separate BIST SA Higher overhead Low testing time parallelism Higher fault coverage SA Chip TPG SA Distributed and embedded BIST Lower overhead Difficult to control In system reconfiguration employed CUT SA TPG Krish Chakrabarty ECE 269 9 STUMPS Architecture Self testing using MISR and PRPG Centralized and separate BIST Multiple scan paths Primary inputs Scan path PRPG Scan path MISR CUT Scan path Primary outputs ECE 269 Krish Chakrabarty 10 5 Built in Logic Block Observer BILBO Reconfigure registers to act in four modes of operation functional parallel load scan serial LFSRs and MISRs Z1 B1 Z2 Z3 B2 Si 0M U 1X D Q Q D Q D Q Q1 Q Q2 Q3 Krish Chakrabarty ECE 269 Q 11 BILBO Operation Modes B1 B2 1 normal mode Z1 Z2 D Q Z3 D Q Q1 D Q2 Q Q3 B1 B2 0 shift register scan mode Si D D D Q Q Q B1 1 B2 0 MISR response mode B1 0 B2 1 LFSR mode ECE 269 Krish Chakrabarty 12 6
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