1 ECE 269 Krish Chakrabarty 1 ECE 269VLSI System TestingKrish ChakrabartyBuilt-In Self-Test (BIST)ECE 269 Krish Chakrabarty 2 Taxonomy BIST methods Off-line On-line Functional Structural Concurrent Non-concurrent2 ECE 269 Krish Chakrabarty 3 Test-Per-Scan BIST (Scan-BIST) Circuit under test Scan chain LFSR Pattern generator LFSR Response monitor • High testing time (one pattern every n+1 cycles) • At-speed testing not possible • Low performance degradation (none beyond scan) • Fairy low overhead ECE 269 Krish Chakrabarty 4 Test-Per-Clock BIST • Suitable for register-based designs • Low testing time (one pattern every cycle) • At-speed testing achieved • Performance degradation (delay on functional paths) • Overhead may be high Circuit under test Input scan register (reconfigured as TPG) Output scan register (reconfigured as SA)3 ECE 269 Krish Chakrabarty 5 BIST Pattern Generators • LFSRs are good pseudorandom pattern generators – Low cost, easy to implement • Suitable for test-per-scan and test-per-clock • LFSR-generated patterns exhibit high degree of randomness (can be measured through statistical correlation tests) ECE 269 Krish Chakrabarty 6 BIST Pattern Generators • For test-per-clock BIST, non-random patterns are often needed, especially for random-pattern-resistant faults • Test length with pseudorandom patterns only is excessive • How to generate non-random patterns? – Use weighted random patterns – Use mapping logic LFSR LFSR Mapping logic4 ECE 269 Krish Chakrabarty 7 BIST Pattern Generators •For scan-BIST, the bits in the LFSR sequence should have low linear correlation and sequence length should be large – Use primitive polynomials – Use longer LFSRs – Use bit-fixing logic LFSR Scan chain LFSR Scan chain Bit-fixing logic From control logic From LFSR Fix-0 Fix-1 Test patterns ECE 269 Krish Chakrabarty 8 BIST Architectures • Centralized and separate BIST – Lower overhead – Lower fault coverage and high testing time – Easy to control and implement Chip CUT CUT Distribution circuit Distribution circuit TPG SA BIST controller5 ECE 269 Krish Chakrabarty 9 BIST Architectures •Distributed and separate BIST – Higher overhead – Low testing time (parallelism) – Higher fault coverage • Distributed and embedded BIST – Lower overhead – Difficult to control – In-system reconfiguration employed Chip CUT CUT TPG SA TPG SA Chip CUT TPG SA TPG SA ECE 269 Krish Chakrabarty 10 STUMPS Architecture •Self-testing using MISR and PRPG • Centralized and separate BIST • Multiple scan paths Scan path Scan path Scan path CUT Primary inputs Primary outputs PRPG MISR6 ECE 269 Krish Chakrabarty 11 Built-in Logic Block Observer (BILBO) •Reconfigure registers to act in four modes of operation: functional (parallel load), scan (serial), LFSRs and MISRs M U X 0 1 D D Q Q Q Q D Q Q Q1 Q2 Q3 Si B2 Z1 Z2 Z3 B1 ECE 269 Krish Chakrabarty 12 BILBO Operation Modes Z1 Q1 Z2 Q2 Z3 Q3 B1 = B2 = 1 (normal mode) D Q Q Q D D D Q D Q Si B1 = B2 = 0 (shift register, scan mode) D Q B1 = 1, B2 = 0 (MISR, response mode), B1 = 0, B2 = 1 (LFSR
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