ECE 269 VLSI System Testing Krish Chakrabarty Lecture 21 Testing for Small Delay Defects I choose a block of marble and chop off everything that I do not need Francoise Auguste Rodin on how he created his statues 1 What Are We After This Class Knowledge of how to efficiently grade test patterns such that test can be selected to increase defect coverage reduce test data volume and decrease test application time The Vital Few The Trivial Many the 80 20 rule 2 1 Motivation Decreasing feature sizes Process technology scales down continuously Very Deep Submicron VDSM designs 3 Background and Motivation High test data volume and test application times Test data volume will be 38x higher in 2015 than today ITRS 2007 Final Draft Test application times will be 17x higher in 2015 than today ITRS 2007 Final Draft Many new types of defects cannot be accurately modeled using existing fault models Need to model the quality of test patterns such that they can be quickly assessed for defect screening Test selection is required to choose the most effective pattern sequences from large test sets Current industry practice for test selection is based on fault grading Computationally expensive Must be repeated for every fault model 4 2 Background and Motivation Contd How can we leverage existing methods for faultoriented test generation Lack of understanding on how best to combine test sets for different fault models i e derive the most effective union of the individual test sets without simply taking all the patterns for each fault model New techniques needed for pattern grading i e evaluate effectiveness of patterns for defect screening Reorder patterns to reduce test time for abort on first fail Reduce pattern count for high volume production test environment and wafer sort Generate select the best patterns for small delay defects 5 A Typical Motivating Scenario Courtesy Phil Nigh IBM Semiconductor chip manufacturer needs to test 1 M copies of a chip with 10 K patterns abort on fail Typically only 2000 of the 10 K patterns are unique fail patterns 70 90 of production test patterns are useless Ferhani et al Stanford IBM data VTS 2008 Guo at al Intel data VTS 2006 Madge et al LSI data ITC 2004 How do we tell which patterns to drop Test economics challenge Majority of the fail patterns e g 1800 out of 2000 occur in the first 5 K patterns Can we predict which 200 patterns of the next 5000 must be applied Currently all 5 K remaining patterns must be applied to get low DPM 6 3 Delay Fault Model Recap Delay fault model Consequence The faulty gate output gets the correct value too late delayed Necessary for deep sub micron DSM designs Stuck at fault model does not cover delay fault effects Delays occur during signal transitions 2 pattern test is required Pattern 1 Create initial logic state Pattern 2 Create a signal transition Small Delay Defects SDDs Delay introduced by the defect is very short 7 Overall Approach Strategy Use output deviations as a surrogate coverage metric for pattern modeling and test grading Use a flexible but general probabilistic fault model to generate a probability map for a logic circuit Target multiple fault sites in a probabilistic manner Compatible with existing test development flows Useful for addressing phenomenon or mechanisms that are not fully understood Premise Higher the deviation better the quality of a test pattern 8 4 Motivation Increasing Defect Rates Resistive shorts bridges Resistive opens All of them are sources of small delay defects Cc 90nm Cc L 10 tOX 3 VTH 30 45nm More effective crosstalk Increased sensitivity to process variations 9 9 Motivation Transition fault ATPG does not target small delay defects SDDs Commercial ATPG tools targeting SDDs timing aware ATPG tools do not consider the real SDD inducing effects Cc 90nm Crosstalk process variations resistive opens Cc 45nm L 3 10 tOX 3 3 VTH 3 30 10 10 5 Shortcomings of Current Methods for Delay Defect Test Stuck at fault model alone not sufficient for high quality test Traditional transition test ATPG does not target small delay defects SDDs Inclined to select short activation paths SDDs are observable on short slack paths long paths of parts Small delay defects Large delay defects Timing aware ATPG tools have now emerged Recent versions of Mentor Graphics FastScan Cadence TrueTime ATPG Synopsys TetraMax Problems High run times for large circuits not addressing process variations Additional delay Sato et al 2005 11 Short Path Sensitization 12 6 Motivation Commercial timing aware ATPG tools are time consuming TimingTiming aware ATPG CPU time relative to TDF ATPG 13 Mentor Graphics Fastscan 13 Motivation Commercial timing aware ATPG tools lead to large number of test patterns 14 14 7 Results on AMD circuits for a commercial TA ATPG tool Selected benchmarks Benchmark Circuit1 Circuit2 Circuit3 Circuit4 Circuit5 Circuit6 Circuit7 of transition faults 769 068 905 908 1 054 368 1 317 564 1 539 220 1 611 570 1 641 856 12 GB memory reserved for all runs 15 15 Results on AMD circuits for a commercial TA ATPG tool Cost Pattern count normalized by n 1 Average 16 increase 8 3x 8 Results on AMD circuits for a commercial TA ATPG tool Cost CPU time normalized by n 1 Average increase 14x 17 Results on AMD circuits for a commercial TA ATPG tool Cost Memory usage normalized by n 1 Average increase 7x 18 9 Pattern Selection Flow Circuit netlist Cell libraries n detect ATPG Large set of base test patterns Output deviations computation Pattern selection and sorting Small set of selected sorted high quality test patterns 19 19 Probabilistic Delay Fault Model Delay defect probability DDP Probability 11 01 DDP Delay DCRITICAL Delay defect probability matrix DDPM for gates OR2 Initial Input State IN0 IN1 Prob 00 01 10 IN0 0 2 0 0 5 IN1 0 1 0 2 0 Inputs 11 0 1 20 20 10 Probabilistic Delay Fault Model and Output Deviations for SDDs Gate Delay Defect Probabilities DDP The probability that the delay of a gate is larger than a delay limit For each input transition the gate has a different delay distribution Set a critical delay limit for the gate Dcrt Dcrt Relaxed limit can be set to MAX delay reported by STA DDP The probability that the gate delay is more than Dcrt for the given input transition Probability 00 10 11 01 Dcrt Dcrt Delay 21 Probabilistic Delay Fault Model and Output Deviations for SDDs Delay Defect Probability Matrix DDPM With DDP for all possible input transitions we can form a matrix of DDPs Delay Defect Probability