1ECE 269: VLSI System Testing Spring 2007 Krish Chakrabarty Term Project Topics January 22, 2007 Outline This handout describes the term project requirements and deadlines, and lists some possible topics for projects. Proposals for projects on other topics are welcome. Project Selection Select a project from the list below, or propose a new project. You must complete a project in order to receive a grade in this course. Projects may be proposed by individual students or by a team of two students. (The latter is recommended only for large programming or design projects.) You will find relevant reference material in the text and in various VLSI CAD journals and conference proceedings (in the library or on the web⎯IEEE Explore, ACM Digital Library, Google Scholar, etc.). Some reading and thinking is necessary in order to select and assess a project; the time spent doing this now will pay off later. Proposal You are required to submit a short proposal (two typed pages maximum, excluding appendices), no later than January 30. Projects will be assigned by the instructor based on the quality of the proposals. The proposal should contain the following: • Titles, author name(s) and e-mail address(es) • Project outline: objectives, work plan, expected results, and other pertinent data • Time schedule listing dates of major “milestones” • Work division (two-person projects only) • References (only those used in preparing the proposal) Every effort will be made to give students their first choice. However, you may be asked to submit a revised or new proposal. You should therefore have a back-up project in mind. Progress reports A brief one-page written progress report will be due on March 8. This report should summarize how the project is progressing, describe any unexpected difficulties encountered, and outline any major changes in the project plan. Oral presentation The class hour on April 24 has been reserved for oral presentations, and where appropriate, for demonstrations. Presentations will be for 15-20 minutes per project. In addition, project proposals must be presented to the class in early February (date to be scheduled). Written report You are required to submit a formal term report due by April 24. This report will be a major factor in determining project grades. The term reports should be of professional quality and be in2the format of a technical report or journal paper. The experimental projects may have shorter reports, with detailed material such as program listings, sample runs, etc. placed in appendices. All reports must contain the following: • Title page • Abstract (summary of report) • Introduction (problem definition, background material, prior work, goals and methods) • Project results in one or more sections • Conclusions (evaluation of results, suggestions for improvement or future work) • References • Appendices (if appropriate) Suggested project topics 1. [Synthesis for transparency for hierarchical and SOC test] A recent synthesis for testability approach relies on the use of transparent paths through large modules. These transparency paths can either be identified after design, or they may be synthesized during design. As part of this project, you are required to survey existing techniques, compare and contrast them, and suggest new directions for further research. You are also encouraged to design transparent circuits using the Synopsys and Mentor DFTAdvisor tools in the VLSI/CAD lab. References: • K. Chakrabarty, “A synthesis-for-transparency approach for hierarchical and system-on-a-chip test”, IEEE Transactions on VLSI Systems, vol. 11, pp. 167-179, April 2003. • T. Yoneda and H. Fujiwara, “Design for consecutive testability of system-on-chip with built-in self-testable cores”, Journal of Electronic Testing: Theory and Applications (JETTA), vol. 18, August/September, pp. 487-501, 2002. • S. Ravi, G. Lakshminarayana and N. K. Jha, “Testing of core-based systems-on-a-chip”, IEEE Transactions on Computer-Aided Design of Circuits and Systems, vol. 20, pp. 426-439, March 2001. • Tomokazu Yoneda, Akiko Shuto, Hideyuki Ichihara, Tomoo Inoue and Hideo Fujiwara, “TAM design and optimization for transparency-based SOC test,” Proc. IEEE 25th VLSI Test Symposium, 2007, to appear. (Ask the instructor for a pre-print.) 2. [Testing for IR-Drop and Power-Supply Noise] As technology shrinks to less than 65 nm and functional density continues to rise, IR-drop and power supply noise (PSN) are becoming significant in the design and test of integrated circuits. Timing closure and functional verification cannot be considered to be complete until pre- and post-layout IR-drop, ground bounce, and PSN effect have been estimated and the appropriate margins applied. These effects have complex interdependencies and conventional design tools do not have the capability to consider all of these effects and their interrelationships concurrently. On-chip monitoring, careful power-ground network planning, worst-case IR-drop prediction, pattern generation for maximum supply noise, path delay analysis considering IR-drop and PSN are among the strategies and methods that should be used. Survey the state-of-the-art in this emerging (and exciting) research area and identify research directions.3References: • N. Ahmed, M. Tehranipoor and V. Jayaram, “Supply Voltage Noise Aware ATPG for Transition Delay Faults,” to appear in IEEE VLSI Test Symposium (VTS'07), 2007. (Ask the instructor for a pre-print.) • N. Ahmed, M. Tehranipoor and V. Jayaram, “A Novel Framework for Faster-than-at-Speed Delay Test Considering IR-Drop Effects,” in Proc. IEEE Int. Conf. on Computer-Aided Design (ICCAD'06), 2006. • Debasis Mitra, Subhasis Bhattacharjee, Susmita Sur-Kolay, Bhargab B. Bhattacharya, Sujit T. Zachariah, Sandip Kundu, "Test Pattern Generation for Power Supply Droop Faults", Proc. IEEE Int. Conf. VLSI Design, 2006. 3. [Test planning for power-conscious wafer-level test during burn-in] This project will be supervised by Sudarshan Bahukudumbi, E-mail: [email protected] There is an ever increasing demand for cost efficient and reliable manufacturing of semiconductor devices. Combining the test and the burn-in process at the wafer-level is one such technique which reduces the test cost by offloading the structural test sequence to the wafer-level. This technique increases the resources of the full-speed ATE to perform