1ECE 269Krish Chakrabarty1ECE 269VLSI System TestingKrish ChakrabartyLecture 2:Test Process and EquipmentECE 269Krish Chakrabarty2Lecture 2VLSI Testing Process and Equipment• Motivation• Types of Testing• Test Specifications and Plan• Test Programming• Test Data Analysis• Automatic Test Equipment• Parametric Testing• Summary2ECE 269Krish Chakrabarty3Motivation• Need to understand some Automatic Test Equipment (ATE) technology– Influences what tests are possible– Serious analog measurement limitations at high digital frequency or in the analog domain– Need to understand capabilities for digital logic, memory, and analog test in System-on-a-Chip (SOC) technology• Need to understand parametric testing– Used to take setup, hold time measurements– Use to computeVIL, VIH, VOL, VOH, tr, tf, td, IOL, IOH, IIL, IIHECE 269Krish Chakrabarty4Types of Testing• Verification testing, characterization testing, or design debug– Verifies correctness of design and of test procedure – usually requires correction to design• Manufacturing testing– Factory testing of all manufactured chips for parametric faults and for random defects• Acceptance testing (incoming inspection)– User (customer) tests purchased parts to ensure quality3ECE 269Krish Chakrabarty5Testing PrincipleECE 269Krish Chakrabarty6Automatic Test Equipment Components• Consists of:– Powerful computer– Powerful 32-bit Digital Signal Processor (DSP) for analog testing– Test Program (written in high-level language) running on the computer– Probe Head (actually touches the bare or packaged chip to perform fault detection experiments)– Probe Card or Membrane Probe (contains electronics to measure signals on chip pin or pad)4ECE 269Krish Chakrabarty7Characterization Test• Worst-case test– Choose test that passes/fails chips– Select statistically significant sample of chips– Repeat test for every combination of 2+ environmental variables– Plot results in Schmoo plot– Diagnose and correct design errors• Continue throughout production life of chips to improve design and process to increase yieldECE 269Krish Chakrabarty8Schmoo Plot5ECE 269Krish Chakrabarty9Manufacturing Test• Determines whether manufactured chip meets specs• Must cover high % of modeled faults• Must minimize test time (to control cost)• No fault diagnosis• Tests every device on chip• Test at speed of application or speed guaranteed by supplierECE 269Krish Chakrabarty10Burn-in or Stress Test• Process:– Subject chips to high temperature & over-voltage supply, while running production tests• Catches:– Infant mortality cases – these are damaged chips that will fail in the first few days of operation – causes bad devices to actually fail before chips are shipped to customers– Freak failures6ECE 269Krish Chakrabarty11Types of Manufacturing Tests• Wafer sort or probe test – done before wafer is scribed and cut into chips– Includes test site characterization – specific test devices are checked with specific patterns to measure:• Gate threshold• Polysilicon field threshold• Poly sheet resistance, etc.• Packaged device testsECE 269Krish Chakrabarty12Sub-types of Tests• Parametric – measures electrical properties of pin electronics – delay, voltages, currents, etc. –fast and cheap• Functional – used to cover very high % of modeled faults – test every transistor and wire in digital circuits – long and expensive7ECE 269Krish Chakrabarty13Two Different Meanings of Functional Test• ATE and Manufacturing World – any vectors applied to cover high % of faults during manufacturing test• Automatic Test-Pattern Generation World –testing with verification vectors, which determine whether hardware matches its specification – typically have low fault coverage (< 70 %)ECE 269Krish Chakrabarty14Test Specifications & Plan• Test Specifications:– Functional Characteristics– Type of Device Under Test (DUT)– Physical Constraints – Package, pin numbers, etc.– Environmental Characteristics – supply, temperature, humidity, etc.– Reliability – acceptance quality level (defects/million), failure rate, etc.• Test plan generated from specifications– Type of test equipment to use– Types of tests– Fault coverage requirement8ECE 269Krish Chakrabarty15Test ProgrammingECE 269Krish Chakrabarty16Test Data Analysis• Uses of ATE test data:– Reject bad DUTs– Fabrication process information– Design weakness information• Devices that did not fail are good only if tests covered 100% of faults• Failure mode analysis (FMA)– Diagnose reasons for device failure, and find design and process weaknesses– Allows improvement of logic & layout design rules9ECE 269Krish Chakrabarty17ADVANTEST Model T6682 ATEECE 269Krish Chakrabarty18T6682 ATE Block Diagram10ECE 269Krish Chakrabarty19T6682 ATE Specifications• Uses 0.35 μm ICs• 1024 pin channels• Speed: 250, 500, or 1000 MHz• Timing accuracy: +/- 200 ps• Drive voltage: -2.5 to 6 V• Clock/strobe accuracy: +/- 870 ps• Clock settling resolution: 31.25 ps• Pattern multiplexing: write 2 patterns in one ATE cycle• Pin multiplexing: use 2 pins to control 1 DUT pinECE 269Krish Chakrabarty20Pattern Generation• Sequential pattern generator (SQPG): stores 16 Mvectorsof patterns to apply to DUT, vector width determined by # DUT pins• Algorithmic pattern generator (ALPG): 32 independent address bits, 36 data bits– For memory test – has address descrambler– Has address failure memory• Scan pattern generator (SCPG) supports JTAG boundary scan, greatly reduces test vector memory for full-scan testing– 2 Gvector or 8 Gvector sizes11ECE 269Krish Chakrabarty21Response Checking and Frame Processor• Response Checking:– Pulse train matching – ATE matches patterns on 1 pin for up to 16 cycles– Pattern matching mode – matches pattern on a number of pins in 1 cycle– Determines whether DUT output is correct, changes patterns in real time• Frame Processor – combines DUT input stimulus from pattern generators with DUT output waveform comparison • Strobe time – interval after pattern application when outputs sampledECE 269Krish Chakrabarty22Probing• Pin electronics (PE) – electrical buffering circuits, put as close as possible to DUT• Uses pogo pin connector at test head• Test head interface through custom printed circuit board to wafer prober (unpackaged chip test) or package