EECS 40 Spring 2003 Lecture 24 S Ross Lecture 24 Today we will Review charging of output capacitance origin of gate delay Calculate output capacitance Discuss fan out Discuss complementary nature of CMOS EECS 40 Spring 2003 Lecture 24 S Ross ORIGIN OF GATE DELAY When the inputs A and B change such that the output F changes VDD A S S PMOS1 PMOS2 F B NMOS1 S NMOS2 S the output cannot change instantaneously the output capacitance must be charged or discharged This is GATE DELAY EECS 40 Spring 2003 Lecture 24 S Ross REVIEW PULL DOWN DEVICES In our logic circuits the NMOS transistors have Gate terminal connected to VIN Source terminal connected to ground directly or through another NMOS This means When VIN is high NMOS transistors are on They help pull down VOUT to ground by conducting current to discharge the output capacitance When VIN is low NMOS transistors are off They act as open circuits from source to drain EECS 40 Spring 2003 Lecture 24 S Ross REVIEW PULL UP DEVICES In our logic circuits the PMOS transistors have Gate terminal connected to VIN Source terminal connected to VDD directly or through another PMOS This means When VIN is low PMOS transistors are on They help pull up VOUT to VDD by conducting current to charge the output capacitance When VIN is high PMOS transistors are off They act as open circuits from source to drain EECS 40 Spring 2003 Lecture 24 S Ross REVIEW MODEL FOR GATE DELAY ANALYSIS There is a model for the behavior of transistors in a CMOS logic circuit to analyze charging discharging of the output capacitance VIN 0 for NMOS VIN VDD for PMOS D G R S The resistance R is the effective resistance for the device during the first half of the transition Each device can have different R VIN VDD for NMOS VIN 0 for PMOS D G R S EECS 40 Spring 2003 Lecture 24 S Ross REVIEW CALCULATING EFFECTIVE RESISTANCE ID N Consider pull down when VOUT must go from VDD to 0 V VDD t tp ID N IDSAT N t 0 ID N IDSAT N RP VOUT VDD VDD 2 VDD VDS N We calculate RN by averaging the values of VDS N ID N at the beginning and ending of delay RN VDD IDSAT N RP VDD IDSAT P RN EECS 40 Spring 2003 Lecture 24 S Ross CALCULATING OUTPUT CAPACITANCE Two major sources of capacitance 1 The transistor gates in the next stage 2 The metal connection to the next stage Both can be computed using the parallel plate capacitor formula k 0 C A d A is the area of the plates k is the dielectric constant of the insulator in between the plates e0 is the permittivity of free space and d is the distance in between the plates k 0 since this is fixed by fabrication process We denote COX d EECS 40 Spring 2003 Lecture 24 S Ross CALCULATING OUTPUT CAPACITANCE Each transistor gate terminal attached to the output contributes a gate capacitance CG W L COX where W and L are the channel dimensions and COX is the capacitance of the gate per unit area parameters from ID vs VDS Each metal connection at the output contributes a capacitance also given by the parallel plate capacitor formula but with different length width and capacitance per unit area k 0 CI WI LI WI LI COX I d EECS 40 Spring 2003 Lecture 24 S Ross EXAMPLE VDD VDD S S S VOUT1 VOUT2 VIN S S S Suppose that VIN was logic 1 for a long time and then switches to logic 0 at t 0 Find the propagation delay through the inverter EECS 40 Spring 2003 Lecture 24 S Ross EXAMPLE Use VDD 5 V VTH N VTH P 1 V COX 5 fF m2 for both transistors L 2 m for both transistors W 2 m for both transistors 0 for both transistors Calculate the effective N 50000 mm2 V s resistance and total output P 25000 mm2 V s capacitance due to gate and WI 2 m interconnect capacitance LI 200 m COX I 0 1 fF m2 EECS 40 Spring 2003 Lecture 24 S Ross EXAMPLE Since VIN is now low VOUT1 must go from low to high Pull up VDD RP VDD S VOUT VDD VIN 0V S RN RP is the resistance involved in the charging EECS 40 Spring 2003 Lecture 24 S Ross EXAMPLE RP VDD IDSAT P RP 5 V W L P COX VGS P VTH P 2 RP 5 V 2 m 2 m 25000 mm2 Vs 5 fF m2 5 V 1V 2 RP 1 875 k Now calculate COUT There are 4 transistor gates attached to inverter output and one wire connecting the inverter output to the NAND input COUT 4 CG CI EECS 40 Spring 2003 Lecture 24 S Ross EXAMPLE CG W L COX 2 m 2 m 5 fF m2 20 fF CI WI LI COX I 2 m 200 m 0 1 fF m2 40 fF COUT 4 CG CI 4 20 fF 40 fF 100 fF tP 0 69 RP COUT 0 69 1 875 k 100 fF 129 ps EECS 40 Spring 2003 Lecture 24 S Ross FAN OUT Consider our previous example Suppose that we connected N NAND gates to the output of the inverter Each NAND gate adds 4 more gate capacitances and another interconnect capacitance COUT N 4 CG CI 100 N fF tp 129 N ps The fan out or number of logic gates that can be attached to an output is limited by propagation delay considerations EECS 40 Spring 2003 Lecture 24 S Ross LOOKING AT CMOS CIRCUITS One can often see the logical operation in a CMOS circuit by looking at either the top or bottom half of the circuit VDD A B C F B A For example looking at the top half of this circuit we see that the output will be connected to VDD F is high when B OR C is low AND A is low C F B C A EECS 40 Spring 2003 Lecture 24 S Ross LOOKING AT CMOS CIRCUITS The bottom half of the circuit always results in the same equation as the top half just rewritten via DeMorgan that s why output is always defined VDD A B C F B A C Looking at the bottom half of this circuit we see that the output will be connected to ground F is low when B AND C are high OR A is high F BC A F BC A
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