Slide 1Slide 2Slide 3Slide 4Slide 5Slide 6Slide 7Slide 8Slide 9Slide 10Slide 11Slide 12Slide 13Slide 14Slide 15Slide 16S. RossEECS 40 Spring 2003 Lecture 24Today we will• Review charging of output capacitance (origin of gate delay)• Calculate output capacitance• Discuss fan-out• Discuss “complementary” nature of CMOSLecture 24S. RossEECS 40 Spring 2003 Lecture 24AFBSSSSPMOS1NMOS1PMOS2NMOS2VDDORIGIN OF GATE DELAYThis is GATE DELAY.When the inputs A and B change such that the output F changes,the output cannot change instantaneously; the output capacitance must be charged or discharged.S. RossEECS 40 Spring 2003 Lecture 24In our logic circuits, the NMOS transistors haveREVIEW: PULL-DOWN DEVICES•Gate terminal connected to VIN•Source terminal connected to ground directly, or through another NMOSThis means•When VIN is high, NMOS transistors are “on”. They help pull-down VOUT to ground, by conducting current to discharge the output capacitance.•When VIN is low, NMOS transistors are “off”. They act as open circuits from source to drain.S. RossEECS 40 Spring 2003 Lecture 24In our logic circuits, the PMOS transistors haveREVIEW: PULL-UP DEVICES•Gate terminal connected to VIN•Source terminal connected to VDD directly, or through another PMOSThis means•When VIN is low, PMOS transistors are “on”. They help pull-up VOUT to VDD, by conducting current to charge the output capacitance.•When VIN is high, PMOS transistors are “off”. They act as open circuits from source to drain.S. RossEECS 40 Spring 2003 Lecture 24There is a model for the behavior of transistors in a CMOS logic circuit to analyze charging/discharging of the output capacitance.DGSVIN = VDD (for NMOS)VIN = 0 (for PMOS)DGSREVIEW: MODEL FOR GATE DELAY ANALYSISRRVIN = 0 (for NMOS)VIN = VDD (for PMOS)The resistance R is the effective resistance for the device during the first half of the transition.Each device can have different R!S. RossEECS 40 Spring 2003 Lecture 24REVIEW: CALCULATING EFFECTIVE RESISTANCEVDS(N)ID(N)VDDVDD/2t=0ID(N) ≈ IDSAT(N)t=tpID(N) ≈ IDSAT(N)VOUTVDDVDDConsider pull-down, when VOUT must go from VDD to 0 V.RNRPWe calculate RN by averaging the values of VDS(N)/ID(N) at the beginning and ending of delay.RN = ¾ VDD / IDSAT(N)RP = -¾ VDD / IDSAT(P)S. RossEECS 40 Spring 2003 Lecture 24CALCULATING OUTPUT CAPACITANCETwo major sources of capacitance:1. The transistor gates in the next stage2. The metal connection to the next stageBoth can be computed using the parallel plate capacitor formula:dkAC0A is the area of the plates, k is the dielectric constant of the insulator in between the plates, e0 is the permittivity of free space, and d is the distance in between the plates.dkC0OXWe denotesince this is fixed by fabrication process.S. RossEECS 40 Spring 2003 Lecture 24Each transistor gate terminal attached to the output contributes a gate capacitanceOXGCLWC where W and L are the channel dimensions and COX is the capacitance of the gate per unit area (parameters from ID vs. VDS).)I(OXII0IIICLWdkLWC Each metal connection at the output contributes a capacitance also given by the parallel plate capacitor formula, but with different length, width, and capacitance per unit area.CALCULATING OUTPUT CAPACITANCES. RossEECS 40 Spring 2003 Lecture 24EXAMPLESVDD SVOUT1VOUT2SSSSVDDVINSuppose that VIN was logic 1 for a long time, and then switches to logic 0 at t = 0. Find the propagation delay through the inverter.S. RossEECS 40 Spring 2003 Lecture 24UseVDD = 5 VVTH(N) = -VTH(P) = 1 VCOX = 5 fF/µm2 for both transistorsL = 2 µm for both transistorsW = 2 µm for both transistors= 0 for both transistorsµN= 50000 mm2 / (V s)µP= 25000 mm2 / (V s)WI = 2 µmLI = 200 µmCOX(I) = 0.1 fF/µm2EXAMPLECalculate the effective resistance and total output capacitance due to gate and interconnect capacitance.S. RossEECS 40 Spring 2003 Lecture 24EXAMPLESince VIN is now low, VOUT1 must go from low to high. Pull-up SSVIN= 0 VVDD VOUTVDDVDDRNRPRP is the resistance involved in the charging.S. RossEECS 40 Spring 2003 Lecture 24EXAMPLERP = - ¾ VDD / IDSAT(P)RP = - ¾ (5 V) / (W/L P COX (VGS(P) – VTH(P))2 )RP = - ¾ (5 V) / (2m/2m 25000 mm2/Vs 5 fF/m2 (-5 V – -1V)2 )RP = 1.875 kNow calculate COUT:There are 4 transistor gates attached to inverter output, and one wire connecting the inverter output to the NAND input.COUT = 4 CG + CIS. RossEECS 40 Spring 2003 Lecture 24EXAMPLECG = W L COX = (2 m)(2 m)(5 fF/m2) = 20 fF CI = WI LI COX(I) = (2 m)(200 m)(0.1 fF/m2) = 40 fF COUT = 4 CG + CI = (4)20 fF + 40 fF = 100 fFtP = 0.69 RP COUT = 0.69 (1.875 k) (100 fF) = 129 psS. RossEECS 40 Spring 2003 Lecture 24FAN-OUTConsider our previous example.Suppose that we connected N NAND gates to the output of the inverter.Each NAND gate adds 4 more gate capacitances and another interconnect capacitance.COUT = N(4 CG + CI) = 100 N fFtp = 129 N psThe fan-out, or number of logic gates that can be attached to an output, is limited by propagation delay considerations.S. RossEECS 40 Spring 2003 Lecture 24LOOKING AT CMOS CIRCUITSABCABCVDDFOne can often “see” the logical operation in a CMOS circuit by looking at either the top or bottom half of the circuit.For example, looking at the top half of this circuit, we see that the output will be connected to VDD (F is high) when:(B OR C is low) AND A is lowF = (B + C) AS. RossEECS 40 Spring 2003 Lecture 24LOOKING AT CMOS CIRCUITSABCABCVDDFThe bottom half of the circuit always results in the same equation as the top half, just rewritten via DeMorgan (that’s why output is always defined). Looking at the bottom half of this circuit, we see that the output will be connected to ground (F is low) when:(B AND C are high) OR A is highF = B C + AF = B C +
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