UNIVERSITY OF CALIFORNIA AT BERKELEY College of Engineering Department of Electrical Engineering and Computer Science R W Brodersen Mike Chen Design Problem 4 Due 5 11 04 EECS 140 Spring 2004 1 Design Specification You are asked to design an operational amplifier used in switched capacitor circuit shown in Figure 1 Notice that the amplifier is labeled Gm it is actually an operational trans conductance amplifier OTA since it does not drive a resistive load but a capacitive load The practical implication is that there is no need for an output stage with a low output resistance which is why the sharp end in the amplifier symbol is missing in Figure 1 The available circuit components are NMOS transistors PMOS transistors or resistors Ideal sources can only be used to generate the supply voltages not to generate bias currents or voltages The design specifications are as following Lmin 0 13 m Wmin nmos 0 15 m Wmin pmos 0 15 m W and L has to be integer multiple of 0 01 m Nominal Vdd 0 6 V Vss 0 6 V CL CF 250 fF CS 500 fF Vin peak peak voltage swings 0 45V You are free to choose input common mode voltage You can apply input offset voltage 1mV within your circuit sp 5pts settling accuracy is 0 1 with settling time 20 ns over 5 power supply 15pts Adm Total differential mode gain Vout Vid 6 000 over the entire output swing range 0 45V to 0 45V and 5 power supply 10pts Acm Total common mode gain Vout Vic 0 1 10pts Area 1 000 m2 The design goal is to 10pts Minimize settling time nsec 5pts Minimize the power consumption Watts nominal Vdd and Vss CF Vin Cs Vdd Vout Gm VIC Vss CL Figure 1 The closed loop gain of the circuit is very close to CS CF 2 Thus for a 0 45 V peakto peak input voltage range the peak to peak output voltage range should be 0 9 V You are allowed to add an input offset voltage to set your nominal DC output voltage at middle rail 0 V The amplifier should be able to handle the range of common mode signals resulting from the 0 45 V signal at the input of the overall circuit You are free to choose the common mode reference VIC The settling is measured for a step at the input going from 0 to Vin pp 2 The settling accuracy of 0 1 includes both dynamic and static settling error 2 Area Calculation Calculate the area by adding up the gate area W L of all the transistors and the area of the resistors For the transistors the minimum L is 0 13 m and the minimum W is 0 15 m For the resistors the minimum W and L are 0 5 m the sheet resistance is 250 square the capacitor density is 5 fF um 2 You are allowed to tie the bulk of any transistor to the source instead of to the positive or negative supply but at the cost of an area penalty If you choose to tie the bulk to the source the area of the transistor should be doubled 3 Device Models http bwrc eecs berkeley edu classes ee140 dp model ee140 sp The device models are encapsulated in a sub circuit use x1 d g s b nmos w 10u l 0 13u x2 d g s b pmos w 10u l 0 13u to instantiate an NMOS and a PMOS transistor respectively you have to use the prefix x instead of m The reason for using a subcircuit is to allow to decrease with increasing transistor length The output resistance parameter will stay the same as before for minimum length transistors Lmin 0 13 m but will decrease with increasing L drawn L not effective L Since the output resistance is proportional to 1 the output resistance increases with increasing L Since we are using level 2 device model it is worthwhile to calculate level 1 parameters of the device model for your hand calculations Ref problem 1 of HW1 extracting K etc A transistor characterization tool called tchar is kindly provided by Ian O Donnell You can run from your UNIX account perl home ff ee140 tchar tchar140 pl For this design problem only look at the model with proc TT and temp 25 4 Run testbench Perform dc operation point AC and small signal transfer function analysis Testbench 1 1 Closed loop transient response for step input 0 to Vstep and 0 to Vstep Purpose check specs for tsettle within settling accuracy 2 Vary the power supply by 5 and re simulate Testbench 2 1 Closed loop frequency response Purpose check closed loop gain and 3dB bandwidth to help your design Testbench 3 1 Open loop differential mode frequency response with and without loading Purpose check Adm unity gain bandwidth and phase margin to help your design 2 DC sweeps over entire output swing range Purpose check if Adm meets the spec over output swing 3 Vary the power supply by 5 and re simulate Testbench 4 1 Open loop common mode frequency response with and without loading Purpose check if Acm meets the spec 2 Vary the power supply by 5 and re simulate Usage put testbench 1 4 dp4 sp model ee140 sp circuit sp parameters sp in the same directory and run hspice testbench dp4 sp o testbench dp4 There is also circuit demo sp ideal OTA for you to play with 5 What to include in your report http bwrc eecs berkeley edu classes ee140 dp guidelines dp4 pdf 6 Grading 100 points total 45 points for conciseness and clearness of the report 40 points for meeting the specifications 15 points for how well you optimize the goals
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