EE40 Lecture 17 Josh Hug 8 04 2010 EE40 Summer 2010 Hug 1 Logistics HW8 will be due Friday Mini midterm 3 next Wednesday 80 160 points will be a take home set of design problems which will utilize techniques we ve covered in class Handed out Friday Due next Wednesday Other 80 160 will be an in class midterm covering HW7 and HW8 Final will include Friday and Monday lecture Midterm won t Design problems will provide practice EE40 Summer 2010 Hug 2 Project 2 Booster lab actually due next week For Booster lab ignore circuit simulation though it may be instructive to try the Falstad simulator Project 2 due next Wednesday Presentation details to come won t be mandatory but we will ask everyone about their circuits at some point EE40 Summer 2010 Hug 3 Project 2 For those of you who want to demo Project 2 we ll be doing demos in lab on Wednesday at some point Will schedule via online survey EE40 Summer 2010 Hug 4 CMOS NMOS Design Correction Sent by email My on the fly explanation was correct but not the most efficient way If your FET circuit is implementing a logic function with a bar over it i e Then don t put an inverter at the output it just makes things harder and less efficient Sorry on the fly explanations can be dicey EE40 Summer 2010 Hug 5 CMOS CMOS Summary No need for a pull up or pull down resistor Though you can avoid this even with purely NMOS logic see HW7 Greatly reduced static power dissipation vs our simple NMOS only logic In reality MOSFETs are never truly off and static leakage power consumes 50 of chip power Dynamic power is still hugely significant Uses twice the number of transistors as our simple purely NMOS logic EE40 Summer 2010 Hug 6 Tradeoffs in Digital Circuits Processor can do more work per second if is high Increasing and lowering give faster rise and fall times letting us increase Dynamic power and heat in CMOS scales as Subthreshold leakage power and heat gets larger as gets smaller and as heat increases Smarter hardware takes more transistors More area means fewer chips per wafer More transistors means more power consumption EE40 Summer 2010 Hug 7 Model Corner Cases What happens if Real MOSFET model is more complicated Switch can be semi on saturates for large not really a resistor EE40 Summer 2010 Hug 8 Real MOSFET Model If we have time this week we ll discuss a more realistic model of the MOSFET Useful for understanding invalid input voltages in logic circuits More importantly tells us how we can utilize MOSFETs in analog circuits Op amps are built from transistors EE40 Summer 2010 Hug 9 Nonlinear Elements This more realistic MOSFET model is nonlinear MOSFETs are three terminal nonlinear devices We will get back to these briefly on Friday Functionality is similar to what we ve seen before op amps Analysis isn t too bad but will take too long to go through If you re curious see chapters 7 and 8 We ll instead turn to diodes Interesting new function Analysis is easier EE40 Summer 2010 Hug 10 Diode Physical Behavior and Shockley Equation Physical Device N P Symbol I I Quantitative I V characteristics Qualitative I V characteristics I V positive high conduction to VD V negative low conduction EE40 Summer 2010 to Allows significant current flow in only one direction Hug 11 The pn Junction I vs V Equation I V characteristic of PN junctions In EECS 105 130 and other courses you will learn why the I vs V relationship for PN junctions is of the form 1 0 026 where I0 is a constant related to device area and materials used to q electronic charge 1 6 10 19 make the diode k is Boltzman constant and T is absolute temperature 10 12 10 15 A a typical value for I0 is We note that in forward bias I increases exponentially and is in the A mA range for voltages typically in the range of 0 6 0 8V In reverse bias the current is essentially zero EE40 Summer 2010 Hug 12 Shockley Equation for the Diode 1 0 026 For typical values Symbol I volts I amps 1 0 1 0 0 0 1 Real Diodes will eventually become linear for large and for really large they ll die EE40 Summer 2010 0 3 0 6 0 01 0 7 0 49 0 8 23 0 9 1080 Hug 13 Large Voltage Limits of the Diode Qualitative I V characteristics large V Qualitative I V characteristics small V I V positive high conduction I Linear VD VD V negative low conduction EE40 Summer 2010 Diode dies Diode dies Green LEDs in lab Linear for 2 3V Die at 6V Hug 14 Solving diode circuits How do we solve this circuit assuming zoomed in region KCL at the top right node Quantitative I V characteristics RTh I VTh EE40 Summer 2010 V n 1 No algebraic solution Hug 15 Load Line Analysis Method 1 Graph the I V relationships for the non linear element and for the rest of the circuit 2 The operating point of the circuit is found from the intersection of these two curves RTh I I VTh V VTh RTh operating point V h 0 026 1 h EE40 Summer 2010 VTh The I V characteristic of all of the circuit except the non linear element is called the load line Hug 16 Load Line Example Power Conversion Circuits Converting AC to DC Potential applications Charging a battery VI Vm cos wt R Vo Can we use phasors Example on board EE40 Summer 2010 Hug 17 Simple Model of a Diode Just as we did with MOSFETs we will utilize a simpler model Goal Accurate enough that we can design circuits For Diodes we started with the real model and are now simplifying For MOSFETs we started with the simplest model and added complexity Omitted real model for MOSFETs because it s not very intuitive unlike real diodes EE40 Summer 2010 Hug 18 Simpler Diode Model I I A V positive high conduction forward bias VD reverse bias VDon V negative low conduction Symbol I VD V Goal To give us approximately the right answer for most inputs EE40 Summer 2010 Hug 19 Voltage Source Model Circuit symbol I I V characteristic I A VD VS model I forward bias reverse bias VDon VD V VDon VD For a Si pn diode VDon 0 7 V ON When ID 0 VD VDon OFF When VD VDon ID 0 Diode behaves like a voltage source in series with a switch closed in forward bias mode open in reverse bias mode EE40 Summer 2010 Hug 20 How to Analyze Diode Circuits with Method of Assumed States A diode has only two states forward biased ID 0 VD 0 7 V or some other reverse biased ID 0 VD 0 7 V Procedure 1 Guess the state s of the diode s drawing equivalent circuit given diode states 2 Check to see if your resulting voltages …
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