1Lecture 23, Slide 1EECS40, Fall 2003 Prof. KingLecture #23Warning for HW Assignments and Exams:• Make sure your writing is legible !!OUTLINE•MOSFET IDvs. VGScharacteristic• Circuit models for the MOSFET– resistive switch model– small-signal modelReference Reading• Rabaey et al.: Chapter 3.3.2• Howe & Sodini: Chapter 4.5Lecture 23, Slide 2EECS40, Fall 2003 Prof. KingMOSFET IDvs. VGSCharacteristicLong-channel MOSFETVDS= 2.5 V > VDSATShort-channel MOSFETVDS= 2.5 V > VDSAT• Typically, VDSis fixed when IDis plotted as a function of VGS2Lecture 23, Slide 3EECS40, Fall 2003 Prof. KingMOSFET VTMeasurement• VTcan be determined by plotting IDvs. VGS, using a low value of VDS :DSDSTGSnDVVVVLWkI−−′=2ID(A)VGS(V)VT0Lecture 23, Slide 4EECS40, Fall 2003 Prof. KingSubthreshold Conduction (Leakage Current)• The transition from the ON state to the OFF state is gradual. This can be seen more clearly when IDis plotted on a logarithmic scale:• In the subthreshold(VGS< VT) region,This is essentially the channel-source pn junction current.(Some electrons diffuse from thesource into the channel, if thispn junction is forward biased.)∝nkTqVIGSDexpVDS> 03Lecture 23, Slide 5EECS40, Fall 2003 Prof. KingQualitative Explanation for Subthreshold Leakage• The channel Vc(at the Si surface) is capacitivelycoupled to the gate voltage VG:oxdepoxdepoxCCCCCn +=+=⇒ 1 CoxCdep+Vc–VGUsing the capacitive voltage divider formula (Lecture 12, Slide 7):p-type Sin+ poly-Sin+ n+depletion regionVGCIRCUIT MODELDEVICEThe forward bias on the channel-source pnjunction increases withVGscaled by the factor Cox/ (Cox+Cdep)VDGdepoxoxcVCCCV ∆+=∆AdepSidepNWC1∝=εWdepLecture 23, Slide 6EECS40, Fall 2003 Prof. KingSlope Factor (or Subthreshold Swing) S• S is defined to be the inverse slope of the log (ID) vs. VGScharacteristic in the subthreshold region:VDS> 01/S is the slope)10ln(≡qkTnSUnits: Volts per decadeNote that S ≥ 60 mV/decat room temperature:mV 60)10ln( =qkT4Lecture 23, Slide 7EECS40, Fall 2003 Prof. KingVTDesign Trade-Off(Important consideration for digital-circuit applications)• Low VTis desirable for high ON currentIDSAT∝ (VDD - VT)η1 < η< 2where VDDis the power-supply voltage…but high VTis needed for low OFF currentLow VTHigh VTIOFF,high VTIOFF,low VTVGSlog IDS0Lecture 23, Slide 8EECS40, Fall 2003 Prof. KingThe MOSFET as a Resistive Switch• For digital circuit applications, the MOSFET is either OFF (VGS< VT) or ON (VGS= VDD). Thus, we only need to consider two IDvs. VDScurves:1. the curve for VGS< VT2. the curve for VGS= VDDIDVDSVGS= VDD (closed switch)VGS< VT(open switch)Req5Lecture 23, Slide 9EECS40, Fall 2003 Prof. KingEquivalent Resistance Req• In a digital circuit, an n-channel MOSFET in the ON state is typically used to discharge a capacitor connected to its drain terminal:– gate voltage VG= VDD– source voltage VS= 0 V– drain voltage VDinitially at VDD, discharging toward 0 VThe value of Reqshould be set to the value which gives the correct propagation delay (time required for output to fall to ½VDD):Cload−≅DDnDSATnDDeqVIVRλ65143()22TnDDnDSATnVVLWkI −′=Lecture 23, Slide 10EECS40, Fall 2003 Prof. KingTypical MOSFET Parameter Values• For a given MOSFET fabrication process technology, the following parameters are known:– VT (~0.5 V)– Coxand k′(<0.001 A/V2)– VDSAT (≤ 1 V)– λ (≤ 0.1 V-1)Example Reqvalues for 0.25 µm technology (W = L):How can Reqbe decreased?6Lecture 23, Slide 11EECS40, Fall 2003 Prof. KingMOSFET Model for Analog Circuits• For analog circuit applications, the MOSFET is biased in the saturation region, and the circuit is designed to process incremental signals.–A DC operating point is established by the bias voltages VBIASand VDD, such that VDS> VGS – VT– Incremental voltages vsand vdsthat are much smaller in magnitude perturb the operating point– The MOSFET small-signal model is a circuit which models the change in the drain current (id) in response to these perturbationsMOSFET+–+–RDVDDVBIASvsGSSDID + id+VDS+ vds−−+Lecture 23, Slide 12EECS40, Fall 2003 Prof. KingNMOSFET Small-Signal Modelgmvgsro+vgs−id()DDSDoTGSGSDmdsogsmdsDSDgsGSDdIvigVVkLWvigvgvgvvivviiλ≅∂∂≡−′≅∂∂≡+=∂∂+∂∂=SDSGtransconductanceoutput
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