EECS 40 Spring 2003 Lecture 4 Sheila Ross and W G Oldham Copyright Regents of University of California EECS 40 Spring 2003 Lecture 4 Copyright Regents of University of California Sheila Ross and W G Oldham Lecture 4 When we perform a sequence of computations using a digital circuit we switch the input voltages between logic 0 and logic 1 The output of the digital circuit fluctuates between logic 0 and logic 1 as computations are performed 1 EECS 40 Spring 2003 Lecture 4 Sheila Ross and W G Oldham Copyright Regents of University of California 2 EECS 40 Spring 2003 Lecture 4 Copyright Regents of University of California Sheila Ross and W G Oldham We compute with pulses voltage RC Circuits We send beautiful pulses in voltage But we receive lousy looking pulses at the output time time Capacitor charging effects are responsible Every node in a circuit has capacitance to ground and it s the charging of these capacitances that limits real circuit performance speed 3 4 EECS 40 Spring 2003 Lecture 4 Sheila Ross and W G Oldham Copyright Regents of University of California EECS 40 Spring 2003 Lecture 4 Copyright Regents of University of California Sheila Ross and W G Oldham RC Response Internal Model of Logic Gate R V in V out C Behavior of Vout after change in Vin Vout Vout Vin Vout t 0 Vin Vout t 0 0 EECS 40 0 0 time Spring 2003 Lecture 4 0 time 5 Sheila Ross and W G Oldham Copyright Regents of University of California 6 EECS 40 Spring 2003 Lecture 4 Copyright Regents of University of California Sheila Ross and W G Oldham RC Response Derivation R KCL at node out Current into out from the left V in Vin Vout R Current out of out down to ground out C Vout ground C dVout dt KCL Vin Vout R C dVout dt Solution dV out 1 Vin Vout dt RC Time Constant RC Vout t Vin Vout t 0 Vin e t RC 7 8 EECS 40 Spring 2003 Lecture 4 Sheila Ross and W G Oldham Copyright Regents of University of California EECS 40 Spring 2003 Lecture 4 Copyright Regents of University of California Sheila Ross and W G Oldham Charging and Discharging Vout t Vin 1 e t Vout t 0 e t Discharging Vin Vout t 0 Charging Vin Vout t 0 Vout Vout Vin 63 Vin 37 Vout t 0 Vout t 0 63 Vin 37 Vout t 0 Vin Vout t 0 0 0 time time 63 of transition complete after 1 EECS 40 Spring 2003 Lecture 4 9 Sheila Ross and W G Oldham Copyright Regents of University of California 10 EECS 40 Spring 2003 Lecture 4 Copyright Regents of University of California Sheila Ross and W G Oldham Common Cases Transition from logic 0 to logic 1 Transition from logic 1 to logic 0 charging discharging Vout t V1e t Vout t V1 1 e t V1 is logic 1 voltage Vout Vout V1 V1 63 V1 37 V1 0 0 time 0 0 time 11 12 EECS 40 Spring 2003 Lecture 4 Sheila Ross and W G Oldham Copyright Regents of University of California EECS 40 Spring 2003 Lecture 4 Copyright Regents of University of California Sheila Ross and W G Oldham Charging and discharging in RC Circuits The official EE40 Easy Method Method of solving for any node voltage in a single capacitor circuit 1 Simplify the circuit so it looks like one resistor a source and a capacitor it will take another two weeks to learn all the tricks to do this But then the circuit looks like this R Input node 2 The time constant is RC Output node Vout 3 Solve for the capacitor voltage before the transient Vout t 0 C Vin ground 4 Solve the for asymptotic value of capacitor voltage Hint Capacitor eventually conducts no current dV dt dies out asymptotically 5 Sketch the transient It is 63 complete after one time constant 6 Write the equation by inspection 13 EECS 40 Spring 2003 Lecture 4 Sheila Ross and W G Oldham Copyright Regents of University of California 14 EECS 40 Spring 2003 Lecture 4 Copyright Regents of University of California Sheila Ross and W G Oldham Example R 1k C 1pF R Input node Assume Vin has been zero for a long time then steps from zero to 10 V at t 0 Output node Vout C Vin ground At t 0 since Vin has been constant for a long time the circuit is in steady state Capacitor current is zero since dV dt 0 so by KVL Vout t 0 0 Asymptotically the capacitor will have no current so the capacitor voltage will be equal to Vin 10 V resistor will have 0 V The time constant RC 1 ns 10 Vin Vout 6 3V We can plug into the equation and draw the graph 0 Vout t 10 10e t 1 ns 0 1 ns time 15 16 EECS 40 Spring 2003 Lecture 4 Sheila Ross and W G Oldham Copyright Regents of University of California EECS 40 Spring 2003 Lecture 4 Copyright Regents of University of California Sheila Ross and W G Oldham PULSE DISTORTION Vin What if I want to step up the input 0 0 Vin time wait for the output to respond Vout 0 0 Vin then bring the input back down for a different response time Vout 0 17 0 EECS 40 Spring 2003 Lecture 4 18 time Sheila Ross and W G Oldham Copyright Regents of University of California EECS 40 Spring 2003 Lecture 4 Copyright Regents of University of California Sheila Ross and W G Oldham PULSE DISTORTION R Input node The pulse width must be long enough or we get severe pulse distortion Output node O C Vin We need to reach a recognizable logic level ground PW RC 6 5 4 3 2 1 0 Vout Vout 6 5 4 3 2 1 0 PW 10RC 0 1 2 Time 3 4 5 6 5 4 3 2 1 0 Vout PW 0 1RC 0 1 2 Time 3 4 5 0 5 10 Time 15 20 19 25 20 EECS 40 Spring 2003 Lecture 4 Sheila Ross and W G Oldham Copyright Regents of University of California EECS 40 Spring 2003 Lecture 4 Copyright Regents of University of California Sheila Ross and W G Oldham EXAMPLE Suppose a voltage pulse of width 5 s and height 4 V is applied to the input of the circuit at the right Sketch the output voltage Vin R Vout R 2 5 K C 1 nF C First the output voltage will increase to approach the 4 V input following the exponential form When the input goes back down the output voltage will decrease back to zero again following exponential form How far will it increase Time constant RC 2 5 s The output increases for 5 s or 2 time constants It reaches 1 e 2 or 86 of the final value 0 86 x 4 V 3 44 V is the peak value EECS 40 Spring …
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