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1ANNOUNCEMENTS• Final Exam:– When: Wednesday 12/10 12:30-3:30PM– Where: 10 Evans (last names beginning A-R)60 Evans (last names beginning S-Z)– Comprehensive coverage of course material– Closed book; 3 sheets of notes & calculator allowed• For Chunlong’s students (Lab Sections 17 & 20):– Section 17 (Wed 3-6 PM) students should attend an alternate section, to have their Tutebots checked off before Thu. 8 PM– Students in Lab Sections 17 & 20 (Wed 3-6 PM & Thu 5-8 PM) can receive their deposit checks back next week.• Prof. King’s Office Hours tomorrow: 1-5 PM, 476 CoryFinal Exam Topics1. Circuit analysis2. Equivalent circuits3. Op-amp circuits4. First-order circuits / transient response5. Semiconductor properties, pn diodes6. MOSFET devices and circuits7. Logic circuits (including delay analysis)8. CMOS process & layoutMicroelectronics Technology in the 21stCenturyOutline• Introduction• Scaling Si Transistors to the Limit• Beyond Scaling• ConclusionReference ReadingRabaey et al.: Section 2.5.2The growth of the semiconductor industry has been tied to transistor scalingIC Technology AdvancementTechnology ScalingInvestmentBetter Performance/CostMarket Growth2000 2005 2010 2015 2020110100GATE LENGTH (nm)YEAR LOW POWER HIGH PERFORMANCEITRS 2001 Projection$141B in 2002Intel’s 90 nm CMOS TechnologyUsed for volume manufacturing of ICson 300 mm wafers beginning 4Q03• Lg= 50 nm• Tox= 1.2 nm• Strained Si channel14 nm CMOS TransistorsHokazono et al., Toshiba Corporation, presented at the International Electron Devices Meeting (San Francisco, CA) Dec. ‘02• 1.3 nm SiOxNygate dielectric•Poly-Si0.9Ge0.1gate2SubstrateGateSource DrainMetal-Oxide-Semiconductor Field-Effect Transistor:Bulk-Si MOSFET Scaling• Leakage current is the main challenge to scaling• To suppress leakage, we need to employ:– Higher body doping Æ lower carrier mobility, higher junction capacitance, increased junction leakage – Thinner gate dielectric Æ higher gate leakage– Ultra-shallow S/D junctions Æ higher RseriesLeffNsubXjLgToxDesired characteristics:• High ON current (Idsat)• Low OFF currentOutline• Introduction• Scaling Si Transistors to the Limit• Beyond Scaling• ConclusionSource DrainGateBulkMOSFETAdvanced MOSFET Structures• Must control leakage in order to scale down Lg• Most of the leakage occurs far from the SiO2interfaceLet’s get rid of it!Source DrainGateSource DrainGateThin-BodyMOSFETSource DrainGateBuried OxideSubstrateSOIWaferThin-Body MOSFETsCommon feature: A thin body, such that no conduction path is far from the gateUltra-Thin BodyGateGateSilicon SubstrateSource DrainTBOXTSiSiO2SOIDouble GateSource DrainGate 1Gate 1VgToxTSiSOIGate 2Gate 2Ultra-Thin-Body MOSFET• Lg= 12 nm• Tox= 2 nm• UTB suppresses leakage • Thick S/D => low Rseries1.E-121.E-101.E-081.E-061.E-041.E-020 0.2 0.4 0.6 0.8 1Gate Voltage [V]Drain Current [A/um]Tsi=8nmTsi=6nmTsi=4nmSimulated Id-VgVds=1VSubthreshold swing S (units: mV/dec)M. Takamiya et al., Proc. 1997 ISDRS, p. 215B. Yu et al., Proc. 1997 ISDRS, p. 623Measured UTB MOSFET Id -VdLg= 80nmTsi= 20nmTox=2.3nmLg= 30nmTsi= 5nmTox=2.1nmGood Idsatachieved with thick S/D structureY.-K. Choi et al., IEDM 1999-1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.001002003004005006007008000100200300400500600700800NMOSPMOS0.25V0.4V0.55V0.7V0.85VVg-Vt=1.0V-0.1V-0.3V-0.5V-0.7V-0.9VVg-Vt=-1.1V Drain Current, |Id| [mA/mm]Drain Voltage, Vd [V]3• Issues for bulk-Si MOSFET scaling obviated– Body does not need to be heavily doped– Toxdoes not need to be scaled as aggressively– Ultra-shallow S/D junction formation is not an issue• Body thickness must be less than ~1/3 x Lg– Formation of uniformly thin body is primary challenge–For TSi< 4 nm, quantum confinement & interface roughness Æ VTvariation and degraded gmK. Uchida et al., IEDM 2002UTB MOSFET ScalingDouble-Gate “FinFET”• Self-aligned gates straddle thin silicon fin• Current flows parallel to wafer surfaceSourceDrainGateSourceDrainGate 2Gate 2Fin Width Wfin= TSiFin Height = Hfin= WGate Length = LgCurrent FlowGate 1Gate 1FinFET Layout• Layout is similar to that of conventional MOSFETBulk-Si MOSFETSourceDrainSourceGateGateSourceDrainSourceFinFETScaling Lgto 10 nm220ÅSiO2capLg=10nmSiO2NiSiPoly-SiSi finB. Yu et al., presented at the 2002 Int’l Electron Devices MeetingtechnologytransferredSourceDrainGateGATESOURCEDRAIN20 nm20 nm10 nm10 nmGATESOURCEDRAIN20 nm20 nm10 nm10 nm10 nm10 nmY.-K. Choi et al., presented at the 2001 Int’l Electron Devices Meeting15nm FinFET fabricated at UC BerkeleyCMOS FinFETs fabricated using standard tools at AMD(optical lithography plus photoresist trimming)10 nm LgFinFET Id-VdB. Yu et al., IEDM Technical Digest, pp. 251-254, 2002• No channel doping is needed in thin-body FETsÆ higher Idsatachieved, dopant fluctuation effects avoidedCircuit Performance ComparisonBulkSG-UTBDG0510 Poly Gate Mid-gap Gate Metal GateLgate=35nm FO4 Inverter Delay [ps]Mixed mode circuit simulations using MEDICI version 4.1L. Chang et al., Proc. IEEE 91 (2003)VTmust be adjusted by gate work function engineering4Molybdenum-Gated FinFETs• Tilted N implantation (60°) used for sidewall gates9 N implantation lowers gate work functionSSTTbodybodyLLgategateWWMoMoPolyPoly--SiSiDDNN++NN++Y.-K. Choi et al., 2002 IEDM-0.8 -0.6 -0.4 -0.2 0.0 0.210-1310-1110-910-710-510-3 Drain Current, Id [A/um]Gate Voltage, Vg[V] Mo MoN( N2=5x1015cm-2)VT shiftLg=80nm, TSi=10nmVds=0.05VMOSFET Scaling to the LimitLg(nm): 65 50 40 30 20 10high-K dielectric (?)GSDSiclassicalGSDSOISiO2Si substrateultra-thin bodymetal gatelow channel dopingdouble-gateGSDSOIGOutline• Introduction• Scaling Si Transistors to the Limit• Beyond Scaling• ConclusionIC Technology Challenges• Limits to transistor scaling exist• Power is an issue of increasing importance– Portable & wireless-communication products require high speed, low cost & very low powerÆAlternative approaches are needed• innovative circuit & system designs• novel semiconductor devices that enable more efficient circuit designs• heterogeneous integrationHeterogeneous IntegrationÆ Enhanced functionality/value of IC productsExample: Integrated Micro-ElectroMechanical Devices– low-power, wireless building blocks• MEMS antennas, microswitches, filters– cooler microprocessors• micropumps, valves, and channels for cooling– smart sensors• environmental monitoring– improved


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Berkeley ELENG 40 - Lecture Notes

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