Final Exam Topics ANNOUNCEMENTS Final Exam When Wednesday 12 10 12 30 3 30PM Where 10 Evans last names beginning A R 60 Evans last names beginning S Z Comprehensive coverage of course material Closed book 3 sheets of notes calculator allowed For Chunlong s students Lab Sections 17 20 Section 17 Wed 3 6 PM students should attend an alternate section to have their Tutebots checked off before Thu 8 PM Students in Lab Sections 17 20 Wed 3 6 PM Thu 5 8 PM can receive their deposit checks back next week 1 2 3 4 5 6 7 8 Circuit analysis Equivalent circuits Op amp circuits First order circuits transient response Semiconductor properties pn diodes MOSFET devices and circuits Logic circuits including delay analysis CMOS process layout Prof King s Office Hours tomorrow 1 5 PM 476 Cory Microelectronics Technology in the 21st Century IC Technology Advancement The growth of the semiconductor industry has been tied to transistor scaling Outline Technology Scaling Introduction Scaling Si Transistors to the Limit Beyond Scaling Conclusion Reference Reading Rabaey et al Section 2 5 2 Investment Better Performance Cost Market Growth 141B in 2002 GATE LENGTH nm 100 ITRS 2001 Projection 10 LOW POWER HIGH PERFORMANCE 1 2000 2005 2010 2015 2020 YEAR Intel s 90 nm CMOS Technology Used for volume manufacturing of ICs on 300 mm wafers beginning 4Q03 14 nm CMOS Transistors Hokazono et al Toshiba Corporation presented at the International Electron Devices Meeting San Francisco CA Dec 02 1 3 nm SiOxNy gate dielectric Poly Si0 9Ge0 1 gate Lg 50 nm Tox 1 2 nm Strained Si channel 1 Bulk Si MOSFET Scaling Outline Leakage current is the main challenge to scaling To suppress leakage we need to employ Introduction Higher body doping lower carrier mobility higher junction capacitance increased junction leakage Scaling Si Transistors to the Limit Thinner gate dielectric higher gate leakage Ultra shallow S D junctions higher Rseries Lg Metal Oxide Semiconductor Field Effect Transistor Beyond Scaling Tox Gate Desired characteristics High ON current Idsat Low OFF current Source Substrate Leff Conclusion Xj Drain Nsub Advanced MOSFET Structures Thin Body MOSFETs Must control leakage in order to scale down Lg Ultra Thin Body Most of the leakage occurs far from the SiO2 interface Let s get rid of it Double Gate Gate SOI Source Gate Thin Body Bulk Source Source MOSFET TBOX TSi Source Tox Silicon Substrate Drain Drain SOI Wafer Buried Oxide Ultra Thin Body MOSFET 1 E 02 Simulated Id Vg Vds 1V 1 E 04 1 E 06 1 E 08 1 E 10 1 E 12 Subthreshold swing S units mV dec Tsi 8nm Tsi 6nm Tsi 4nm 0 0 2 0 4 0 6 0 8 1 Gate Voltage V Drain Current Id mA mm Drain Current A um Tox 2 nm Vg SOI Drain TSi Gate 2 Measured UTB MOSFET Id Vd Lg 12 nm UTB suppresses leakage Thick S D low Rseries Gate 1 Common feature A thin body such that no conduction path is far from the gate Substrate M Takamiya et al Proc 1997 ISDRS p 215 B Yu et al Proc 1997 ISDRS p 623 Drain SiO2 800 700 600 500 400 300 200 PMOS Lg 30nm Tsi 5nm Tox 2 1nm Vg Vt 1 1V 800 Vg Vt 1 0V NMOS 700 Lg 80nm Tsi 20nm 0 85V 600 Tox 2 3nm 500 0 7V 400 0 9V 0 55V 300 Good Idsat achieved with thick S D structure 0 7V 200 0 4V 0 5V 100 0 3V 100 0 25V 0 0 1V 0 1 0 0 8 0 6 0 4 0 2 0 0 0 2 0 4 0 6 0 8 1 0 Drain Voltage Vd V Y K Choi et al IEDM 1999 2 Double Gate FinFET Issues for bulk Si MOSFET scaling obviated Self aligned gates straddle thin silicon fin Current flows parallel to wafer surface Body does not need to be heavily doped Tox does not need to be scaled as aggressively Ultra shallow S D junction formation is not an issue Source Gate Length Lg Body thickness must be less than 1 3 x Lg Formation of uniformly thin body is primary challenge For TSi 4 nm quantum confinement interface roughness VT variation and degraded gm Gate Gate 2 Current Flow K Uchida et al IEDM 2002 Drain Source Gate 1 Drain UTB MOSFET Scaling Fin Height Hfin W Fin Width Wfin TSi Scaling Lg to 10 nm FinFET Layout Gate Layout is similar to that of conventional MOSFET Drain 15nm FinFET fabricated at UC Berkeley GATE Source Gate Drain Source Source Bulk Si MOSFET FinFET NiSi DRAIN Gate Drain Source 20 nm Source Poly Si 220 SiO2 cap 10 nm technology transferred SOURCE Y K Choi et al presented at the 2001 Int l Electron Devices Meeting Si fin Lg 10nm SiO2 B Yu et al presented at the 2002 Int l Electron Devices Meeting CMOS FinFETs fabricated using standard tools at AMD optical lithography plus photoresist trimming 10 nm Lg FinFET Id Vd Circuit Performance Comparison No channel doping is needed in thin body FETs FO4 Inverter Delay ps higher Idsat achieved dopant fluctuation effects avoided B Yu et al IEDM Technical Digest pp 251 254 2002 Mixed mode circuit simulations using MEDICI version 4 1 Poly Gate Mid gap Gate Metal Gate Lgate 35nm 10 5 0 L Chang et al Proc IEEE 91 2003 Bulk SG UTB DG VT must be adjusted by gate work function engineering 3 Molybdenum Gated FinFETs MOSFET Scaling to the Limit Y K Choi et al 2002 IEDM PolySi Mo 10 S N D W Lgate Tbody Drain Current Id A um N high K metal dielectric gate 3 Lg 80nm TSi 10nm Vds 0 05V 5 10 7 10 Lg nm 65 VT shift 11 13 10 40 S 20 10 D classical Si Mo 15 2 MoN N2 5x10 cm 0 8 0 6 0 4 0 2 0 0 Gate Voltage Vg V 30 low channel doping G 9 10 10 50 G S 0 2 Tilted N implantation 60 used for sidewall gates 9 N implantation lowers gate work function Outline Introduction ultra thin body SOI D SiO2 Si substrate G double gate S SOI D G IC Technology Challenges Limits to transistor scaling exist Power is an issue of increasing importance Scaling Si Transistors to the Limit Portable wireless communication products require high speed low cost very low power Beyond Scaling Alternative Conclusion Heterogeneous Integration Enhanced functionality value of IC products Example Integrated Micro ElectroMechanical Devices low power wireless building blocks MEMS antennas microswitches filters approaches are needed innovative circuit system designs novel semiconductor devices that enable more efficient circuit designs heterogeneous integration MEMS Technology Surface Micromachining cross sectional view structural film sacrificial layer cooler microprocessors micropumps valves and channels for cooling Si wafer substrate Mechanical structures can be made using conventional microfabrication techniques Structures are freed by selective removal of sacrificial layer s smart sensors environmental monitoring improved energy efficiency emergency response contamination detection bio chips microfluidics
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