EE40 Lecture 12 Venkat Anantharam 2 20 08 Reading Chap 4 first order circuits EE40 Spring 2008 Slide 1 Venkat Anantharam First Order Circuits vs t vr t R C iL t ic t vc t is t R L vL t KVL around the loop KCL at the node dvc t RC vc t vs t dt EE40 Spring 2008 L diL t iL t is t R dt Slide 2 Venkat Anantharam Response of a Circuit Transient response of a circuit is the portion of the total response that dies to zero as time goes to infinity Steady state response is what remains of the total response after the transient response is removed Natural response of a circuit is the portion of the response due to the initial conditions This is generally part of the transient response except in cases where there is some energy in the initial conditions that cannot dissipate through resistors e g a pure LC oscillator Forced response is the portion of the response due to the forcing function the right hand side of the differential equation that comes from the sources In general this will also have a transient part We will later be mostly interested in the steady state response of circuits to a DC forcing function or more generally a sinusoidal forcing function Note some of this terminology is at variance with your book Your book s definition of forced response for instance is inconsistent EE40 Spring 2008 Slide 3 Venkat Anantharam Natural Response of an RC Circuit Consider the following circuit for which the switch is closed for t 0 and then opened at t 0 Vo Ro C t 0 v R Notation 0 is used to denote the time just prior to switching 0 is used to denote the time immediately after switching The voltage on the capacitor at t 0 is Vo EE40 Spring 2008 Slide 4 Venkat Anantharam Solving for the Voltage t 0 For t 0 the circuit reduces to Vo i Ro C v R Applying KCL to the RC circuit Solution EE40 Spring 2008 v t Vo e t RC Slide 5 Venkat Anantharam Solving for the Current t 0 i Vo Ro C v R v t Voe t RC Note that the current changes abruptly i 0 0 v Vo t RC for t 0 i t e R R Vo i 0 R EE40 Spring 2008 Slide 6 Venkat Anantharam Solving for Power and Energy Delivered t 0 i Vo Ro C v R v t Vo e t RC v 2 Vo2 2 t RC p e R R t t 2 Vo 2 x RC w p x dx e dx R 0 0 1 CVo2 1 e 2 t RC 2 EE40 Spring 2008 Slide 7 Venkat Anantharam Natural Response of an RL Circuit Consider the following circuit for which the switch is closed for t 0 and then opened at t 0 t 0 Io Ro i L R v Notation 0 is used to denote the time just prior to switching 0 is used to denote the time immediately after switching t 0 the entire system is at steady state and the inductor is like short circuit The current flowing in the inductor at t 0 is Io and V across is 0 EE40 Spring 2008 Slide 8 Venkat Anantharam Solving for the Current t 0 For t 0 the circuit reduces to i Io L Ro R v Applying KVL to the LR circuit v t i t R At t 0 i I0 di t At arbitrary t 0 i i t and v t L Solution EE40 Spring 2008 dt i t i 0 e R L t Slide 9 I0e R L t Venkat Anantharam Solving for the Voltage t 0 i t I oe R L t Io Ro L R v Note that the voltage changes abruptly v 0 0 for t 0 v t iR I o Re R L t v 0 I0R EE40 Spring 2008 Slide 10 Venkat Anantharam Solving for Power and Energy Delivered t 0 i t I o e R L t Io Ro L R v p i 2 R I o2 Re 2 R L t t t 0 0 w p x dx I o2 Re 2 R L x dx 1 2 2 R L t LI o 1 e 2 EE40 Spring 2008 Slide 11 Venkat Anantharam Natural Response Summary RL Circuit RC Circuit i L v R C R Inductor current cannot change instantaneously Capacitor voltage cannot change instantaneously i 0 i 0 v 0 v 0 i t i 0 e t v t v 0 e t L time constant R EE40 Spring 2008 Slide 12 time constant RC Venkat Anantharam Digital Signals We send beautiful pulses in voltage We compute with pulses But we receive lousy looking pulses at the output voltage time time Capacitor charging effects are responsible Every node in a real circuit has capacitance it s the charging of these capacitances that limits circuit performance speed EE40 Spring 2008 Slide 13 Venkat Anantharam Pulse Distortion R Vin t Vout C We need to wait for the output to reach a recognizable logic level before changing the input again Pulse width RC Vout Vout 6 5 4 3 2 1 0 Pulse width 10RC 0 1 2 Time 3 EE40 Spring 2008 4 5 6 5 4 3 2 1 0 Vout Pulse width 0 1RC 6 5 4 3 2 1 0 The input voltage pulse width must be large enough otherwise the output pulse is distorted 0 1 2 Time 3 Slide 14 4 5 0 5 10 Time 15 20 25 Venkat Anantharam Example Suppose a voltage pulse of width 5 s and height 4 V is applied to the input of this circuit beginning at t 0 RC 2 5 s Vin R R 2 5 k C 1 nF Vout C First Vout will increase exponentially toward 4 V When Vin goes back down Vout will decrease exponentially back down to 0 V What is the peak value of Vout The output increases for 5 s or 2 time constants It reaches 1 e 2 or 86 of the final value 0 86 x 4 V 3 44 V is the peak value EE40 Spring 2008 Slide 15 Venkat Anantharam First Order Circuits Forced Response vs t vr t R C iL t ic t vc t is t R L vL t KVL around the loop vr t vc t vs t KCL at the node t v t 1 v x dx is t R L dvc t RC vc t vs t dt EE40 Spring 2008 L diL t iL t is t R dt Slide 16 Venkat Anantharam Complete Solution Voltages and currents in a 1st order circuit satisfy a differential equation of the form dx t x t f t dt f t is called the forcing function The complete solution is the sum of any particular solution and the associated complementary solution p c x t x t x t Particular …
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