Midterm 1 Announcements Review session 5 8pm TONIGHT 277 Cory Midterm 1 11 30 1pm on Tuesday July 12 in Dwinelle 145 Material covered in HW1 3 Attend only your second lab slot this week EE40 Summer 2005 Lecture 9 Instructor Octavian Florescu 1 Review Second Order Filter Circuits Band Pass R VS Z R 1 j C j L Low Pass C High Pass L EE40 Summer 2005 Lecture 9 HBP R Z Band HLP 1 j C Z Reject HHP j L Z HBR HLP HHP Instructor Octavian Florescu 2 1 Lecture 9 OUTLINE The operational amplifier op amp Ideal op amp Feedback Unity gain voltage follower circuit Summing difference integrator differentiator active filter Reading Ch 14 EE40 Summer 2005 Lecture 9 Instructor Octavian Florescu 3 The Operational Amplifier The operational amplifier op amp is a basic building block used in analog circuits Its behavior is modeled using a dependent source When combined with resistors capacitors and inductors it can perform various useful functions amplification scaling of an input signal sign changing inversion of an input signal addition of multiple input signals subtraction of one input signal from another integration over time of an input signal differentiation with respect to time of an input signal analog filtering nonlinear functions like exponential log sqrt etc EE40 Summer 2005 Lecture 9 Instructor Octavian Florescu 4 2 Op Amp Terminals 3 signal terminals 2 inputs and 1 output IC op amps have 2 additional terminals for DC power supplies Common mode signal v1 v2 2 Differential signal v1 v2 V Inverting input v2 Non inverting input v1 positive power supply v0 output V negative power supply EE40 Summer 2005 Lecture 9 Instructor Octavian Florescu 5 Op Amp Terminal Voltages and Currents All voltages are referenced to a common node Current reference directions are into the op amp V i1 v1 v2 ic i2 icV io vo Vcc Vcc common node external to the op amp EE40 Summer 2005 Lecture 9 Instructor Octavian Florescu 6 3 Model A is differential gain or open loop gain Ideal op amp A Ri v1 Ro 0 i1 Circuit Model Ro io Ri Common mode gain 0 v v2 v v v vcm 1 1 2 d 2 vo Acm vcm Ad vd v2 i2 vo A v1 v2 Since vo A v1 v2 Acm 0 EE40 Summer 2005 Lecture 9 Instructor Octavian Florescu 7 Model and Feedback Negative feedback Circuit Model connecting the output port to the negative input port 2 Positive feedback connecting the output port to the positive input port 1 v1 i1 Ro io Ri v2 EE40 Summer 2005 Lecture 9 i2 Instructor Octavian Florescu vo A v1 v2 8 4 Summing Point Constraint Check if under negative feedback Small vi result in large vo Output vo is connected to the inverting input to reduce vi Resulting in vi 0 Summing point constraint v1 v2 i1 i2 0 Virtual short circuit Not only voltage drop is 0 which is short circuit input current is 0 This is different from short circuit hence called virtual short circuit EE40 Summer 2005 Lecture 9 Instructor Octavian Florescu 9 Inverting Amplifier Negative feedback checked Use summing point constraint R2 2 R1 v i 2 v0 vin v1 Closed loop gain Av vo vin v1 v2 0 i1 i2 0 Use KCL At Node 2 i vin v 2 vout v 2 R1 R2 vo R2 vo R1 Input impedance vin R1 i RL Ideal voltage source independent of load resistor EE40 Summer 2005 Lecture 9 Instructor Octavian Florescu 10 5 Non Inverting Amplifier Ideal voltage amplifier 2 v0 vo vin v1 v 2 vin i1 i2 0 v2 vin Closed loop gain Av RL R2 R1 Use KCL At Node 2 i v0 v 2 v2 0 R2 R1 A vo R1 R2 vin R1 Input impedance EE40 Summer 2005 Lecture 9 Instructor Octavian Florescu vin i 11 Voltage Follower v0 v2 vin RL R2 0 R1 i v0 v2 v2 0 R2 R1 A vo R1 R2 R 1 2 1 vin R1 R1 EE40 Summer 2005 Lecture 9 Instructor Octavian Florescu 12 6 Example 1 Switch is open v1 v2 i1 0 i3 0 2 i4 R i3 vin R i5 v2 i 2 v1 i 1 vin v1 v1 v2 vin i4 0 i5 0 R v v i 5 0 2 v0 v2 vin R vo A 1 Rin vin i3 R v0 RL Switch is closed v1 v2 0 i1 0 i3 0 vin v2 v v i 5 0 2 R R v0 vin i4 A EE40 Summer 2005 Lecture 9 vo 1 Rin R 2 vin Instructor Octavian Florescu 13 Example 2 Requires to work with 3 full scale of input signals by manual switch vb 0 1 0 10 0 100 V va For each input range the output needs to be 0 10 V The input resistance is 1M R vo 1 2 v1 R1 v1 v2 Design an analog front end circuit to an instrument system vin c b a 2 v0 RL R2 R1 v1 vin Switch at c v1 Ra Rb vin Switch at b Ra Rb Rc v1 Ra vin Switch at a Ra Rb Rc EE40 Summer 2005 Lecture 9 Instructor Octavian Florescu 14 7 Example 2 cont d Rin Ra Rb Rc 1M Max Av 10 1 Av 1 R2 Switch at c R1 R a Rb R a Rb R 1 2 Switch at b 0 1 R a Rb R c R1 R a Rb R c Av 0 1 Ra Ra R 1 2 Switch at a 0 01 R a Rb R c R1 R a Rb R c Ra 10 k Rb 90 k Rc 900 k R2 9 R1 EE40 Summer 2005 Lecture 9 Instructor Octavian Florescu 15 Summing Amplifier v1 R1 R0 v2 R2 v3 R3 EE40 Summer 2005 Lecture 9 v0 Instructor Octavian Florescu 16 8 Difference Amplifier R2 v1 R1 v2 v0 R3 R4 EE40 Summer 2005 Lecture 9 Instructor Octavian Florescu 17 Instructor Octavian Florescu 18 Integrator Want vo K vin dt What is the difference between vin R V0 C EE40 Summer 2005 Lecture 9 9 Differentiator Want R C v0 vin EE40 Summer 2005 Lecture 9 Instructor Octavian Florescu 19 Application Digital to Analog Conversion A DAC can be used to convert the digital representation Binary Analog number output of an audio signal into an analog voltage that is then volts used to drive speakers so that you can hear it 0000 0 Weighted adder D A converter S4 20K S2 40K 5K 80K S1 4 Bit D A Transistors are used as electronic switches EE40 Summer 2005 Lecture 9 S3 8V 10K V0 S1 closed if LSB 1 S2 if next bit 1 S3 if 1 S4 if MSB 1 Instructor Octavian Florescu 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 MSB 5 1 1 5 2 2 5 3 3 5 4 4 5 5 5 5 6 6 5 7 7 5 LSB 20 10 Analog Output V Characteristic of 4 Bit DAC 8 7 6 5 4 3 …
View Full Document
Unlocking...