1Lecture 38, Slide 1EECS40, Fall 2003 Prof. KingLecture #38ANNOUNCEMENTS• Prof. King’s Office Hour today is changed back to 4-5 PM• HW#11, Problem 4: The number of dice per wafer must be rounded down to an integer value!• Reminder: Tutebot projects are due beginning 12/2• HW#12 (short assignment) will be due 12/5• Discussion sections and lab sections will continue as usualOUTLINE• Propagation delay with interconnect • Inter-wire capacitance• Pi model for capacitive coupling• Coupling capacitance effects– loading– crosstalkLecture 38, Slide 2EECS40, Fall 2003 Prof. KingPropagation Delay with InterconnectwirewiredrfanoutwiredrintrinsicdrpCRRCRRCRt)38.069.0( )(69.069.0++++=wirewiredrfanoutwiredrintrinsicdrDpCRRCRRCRt)(69.0 )(69.0 69.0 69.0++++==τUsing the lumped-RC interconnect model:In reality, the interconnect resistance & capacitance aredistributed along the length of the interconnect.Æ The interconnect delay is actually less than RwireCwire:The 0.38 factor accounts for the fact that the wire resistance and capacitance are distributed.2Lecture 38, Slide 3EECS40, Fall 2003 Prof. KingBWire B has additional sidewall capacitance to neighboring wiresCWire C has additional capacitance to the wire above itInterconnect Wire-to-Wire CapacitanceWire A simply has capacitance (Cpp+ Cfringe) to substrateASi substrateoxideLecture 38, Slide 4EECS40, Fall 2003 Prof. KingWiring Examples - Intel ProcessesIntel 0.25µm Process (Al)5 Layers - Tungsten ViasSource: Intel Technical Journal 3Q98Intel 0.13µm Process (Cu)Source: Intel Technical Journal 2Q02k=3.6TungstenPlugsTungstenPlugsAdvanced processes: narrow linewidths, taller wires, close spacing Æ relatively large inter-wire capacitances3Lecture 38, Slide 5EECS40, Fall 2003 Prof. KingEffects of Inter-Wire Capacitance• Capacitance between closely spaced lines leads to two major effects:1. Increased capacitive loading on driven nodes (speed loss)2. Unwanted transfer of signals from one place to another through capacitive coupling “crosstalk”• We will use a very simple model to estimate the magnitude of these effects. In real circuit designs, very careful analysis is necessary.Lecture 38, Slide 6EECS40, Fall 2003 Prof. KingWire 1 has resistance R1Wire 2 has resistance R2There are three capacitances as illustrated12substrateC1C2CCUsing a simple lumped model for each wire we have three capacitances and two resistances C1C2CCR1R2C1C2CCR1R2Which, when redrawn in a plane, has a “π “ shapePi Model for Capacitive Coupling4Lecture 38, Slide 7EECS40, Fall 2003 Prof. KingCoupling Capacitance: Loading EffectA) Coupling to grounded adjacent lineB) Coupling to floating adjacent lineC) Coupling to driven adjacent lineCase C is well-approximated to be the same as case ALecture 38, Slide 8EECS40, Fall 2003 Prof. KingInsert the Pi model:C1and CCare in parallel with the input capacitance of inverter 2, Cin2.This combined C is driven by the output resistance of inverter 1 in series with the line resistance R1C1C2CCR1R221Case A: Coupling to Grounded Line12Wire 1Wire 2()( )211111 inCdroutdrDCCCRRCR ++++=τintrinsic capacitance of Inverter 15Lecture 38, Slide 9EECS40, Fall 2003 Prof. KingC1is in parallel with the series combination of CC and C2. This combined C is driven by the output resistance of inverter 1 in series with the line resistance R112C1C2CCR1R221Case B: Coupling to Floating LineInsert the Pi model:()+++++=22211111 inCCdroutdrDCCCCCCRRCRτWire 1Wire 2Lecture 38, Slide 10EECS40, Fall 2003 Prof. KingSignal from (1) couples to adjacent lineInsert Pi model:12344C1C2CCR1R2213Note that (4) receives both from (3) and from (1). The latter is undesired crosstalk. Similarly, (2) receives signal both from (1) and from (3).Let’s assume (3) is quiet, and (1) is broadcasting…Coupling Capacitance: CrosstalkWire 1Wire 26Lecture 38, Slide 11EECS40, Fall 2003 Prof. King4C1C2CCR1R2213We want to estimate the magnitude of the crosstalk signal at the input to (4). We cannot easily treat this problem exactly, but we can see that:1. The crosstalk signal is attenuated by the capacitive voltage divider CC in series with (C2 || Cin4 ). 2. If CCis very large, about half the signal from (1) is coupled into (4) because of the voltage divider R1+Rdr1in series with R2+Rdr3where Vin4is tapped off at the center.We can solve this two-time-constant problem from the differential equations, but are more likely to use a computer simulation tool.Lecture 38, Slide 12EECS40, Fall 2003 Prof. KingSilicon substrateSiO2ground1. Increase inter-wire spacing (decrease CC)2. Decrease field-oxide thickness (decrease CC/C2)…but this loads the driven nodes and thus decreases circuit speed.3. Place ground lines (or VDDlines) between signal linesApproaches to Reducing
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