Lecture 38 ANNOUNCEMENTS Prof King s Office Hour today is changed back to 4 5 PM HW 11 Problem 4 The number of dice per wafer must be rounded down to an integer value Reminder Tutebot projects are due beginning 12 2 HW 12 short assignment will be due 12 5 Discussion sections and lab sections will continue as usual OUTLINE Propagation delay with interconnect Inter wire capacitance Pi model for capacitive coupling Coupling capacitance effects loading crosstalk EECS40 Fall 2003 Lecture 38 Slide 1 Prof King Propagation Delay with Interconnect Using the lumped RC interconnect model t p 0 69 D 0 69 Rdr Cintrinsic 0 69 Rdr Rwire C fanout 0 69 Rdr Rwire Cwire In reality the interconnect resistance capacitance are distributed along the length of the interconnect The interconnect delay is actually less than RwireCwire t p 0 69 Rdr Cintrinsic 0 69 Rdr Rwire C fanout 0 69 Rdr 0 38 Rwire Cwire The 0 38 factor accounts for the fact that the wire resistance and capacitance are distributed EECS40 Fall 2003 Lecture 38 Slide 2 Prof King 1 Interconnect Wire to Wire Capacitance A B C oxide Si substrate Wire A simply has capacitance Cpp Cfringe to substrate Wire B has additional sidewall capacitance to neighboring wires Wire C has additional capacitance to the wire above it EECS40 Fall 2003 Lecture 38 Slide 3 Prof King Wiring Examples Intel Processes Advanced processes narrow linewidths taller wires close spacing relatively large inter wire capacitances k 3 6 Tungsten Plugs Intel 0 25 m Process Al 5 Layers Tungsten Vias Tungsten Plugs Source Intel Technical Journal 3Q98 Intel 0 13 m Process Cu Source Intel Technical Journal 2Q02 EECS40 Fall 2003 Lecture 38 Slide 4 Prof King 2 Effects of Inter Wire Capacitance Capacitance between closely spaced lines leads to two major effects 1 Increased capacitive loading on driven nodes speed loss 2 Unwanted transfer of signals from one place to another through capacitive coupling crosstalk We will use a very simple model to estimate the magnitude of these effects In real circuit designs very careful analysis is necessary EECS40 Fall 2003 Lecture 38 Slide 5 Prof King Pi Model for Capacitive Coupling There are three capacitances as illustrated Wire 2 has resistance R2 Using a simple lumped model for each wire we have three capacitances and two resistances R2 CC EECS40 Fall 2003 C2 1 2 C2 C1 substrate R1 C1 CC Wire 1 has resistance R1 R1 Which when redrawn in a plane has a shape Lecture 38 Slide 6 R2 CC C1 C2 Prof King 3 Coupling Capacitance Loading Effect A Coupling to grounded adjacent line B Coupling to floating adjacent line C Coupling to driven adjacent line Case C is well approximated to be the same as case A EECS40 Fall 2003 Lecture 38 Slide 7 Prof King Case A Coupling to Grounded Line Wire 1 1 2 Wire 2 Insert the Pi model 2 1 R1 R2 CC C1 C2 intrinsic capacitance of Inverter 1 C1 and CC are in parallel with the input capacitance of inverter 2 Cin2 This combined C is driven by the output resistance of inverter 1 in series with the line resistance R1 D Rdr1Cout1 R1 Rdr1 C1 CC Cin 2 EECS40 Fall 2003 Lecture 38 Slide 8 Prof King 4 Case B Coupling to Floating Line Wire 1 1 2 Wire 2 Insert the Pi model 2 1 R1 R2 C1 is in parallel with the series combination of CC and C2 CC This combined C is driven by the output resistance of inverter 1 in series with the line resistance R1 C2 C1 D Rdr1Cout1 R1 Rdr1 C1 EECS40 Fall 2003 C2CC Cin 2 C2 CC Lecture 38 Slide 9 Prof King Coupling Capacitance Crosstalk Wire 1 1 Signal from 1 couples to adjacent line 2 Wire 2 3 4 Insert Pi model 2 1 R1 R2 3 CC C1 C2 4 Note that 4 receives both from 3 and from 1 The latter is undesired crosstalk Similarly 2 receives signal both from 1 and from 3 Let s assume 3 is quiet and 1 is broadcasting EECS40 Fall 2003 Lecture 38 Slide 10 Prof King 5 2 1 R1 R2 3 CC C1 C2 We want to estimate the magnitude of the crosstalk signal at the input to 4 4 We cannot easily treat this problem exactly but we can see that 1 The crosstalk signal is attenuated by the capacitive voltage divider CC in series with C2 Cin4 2 If CC is very large about half the signal from 1 is coupled into 4 because of the voltage divider R1 Rdr1 in series with R2 Rdr3 where Vin4 is tapped off at the center We can solve this two time constant problem from the differential equations but are more likely to use a computer simulation tool EECS40 Fall 2003 Lecture 38 Slide 11 Prof King Approaches to Reducing Crosstalk 1 Increase inter wire spacing decrease CC 2 Decrease field oxide thickness decrease CC C2 but this loads the driven nodes and thus decreases circuit speed 3 Place ground lines or VDD lines between signal lines ground SiO 2 Silicon substrate EECS40 Fall 2003 Lecture 38 Slide 12 Prof King 6
View Full Document
Unlocking...