EE40 Lecture 15 Josh HugLogisticsMidterm 2Logic Gates and Static DisciplineiClicker WarmupField Effect TransistorSlide 7Slide 8Field Effect Transistor SummaryDiscussion TodayMOSFET ModelSlide 12S Model of the MOSFETBuilding a NAND gate using MOSFETsMOSFET modelingSR Model of the MOSFETNAND with the SR ModelSlide 18Slide 19Another SR Model ExampleSlide 21The power of digital circuitsSlide 23The power of digital circuits (literally)Power ExampleSlide 26Static PowerThe SRC Model of an NMOS TransistorThe SRC ModelSlide 30SRC ModelSRC Model of our 2 InvertersAnalysis of SRC ModelSlide 34Slide 35Timing Analysis of the SRC modelSlide 37Slide 38Fall TimeSlide 40Slide 41Slide 42Slide 43Propagation DelayReminder of Where We StartedUsing Propagation DelaysPropagation DelaysBonus Question for CS61C VeteransPowerPoint PresentationPower in the SRC ModelDynamic Power in NMOS CircuitsSlide 52Dynamic PowerProblem SetupSolutionAvoiding Static Power LossPMOS TransistorAnything logical we can do with NMOS…Analysis of PMOS LogicCMOS InverterSlide 61Slide 62Static Power in CMOSDynamic Power in CMOSSlide 65Slide 66CMOSImplementation of Complex Gates Using NMOS and CMOSThat’s it for todayExtra SlidesSR Model of the PMOS MOSFET1EE40 Summer 2010HugEE40Lecture 15 Josh Hug7/30/20102EE40 Summer 2010HugLogistics•HW7 due Tuesday•HW8 will be due next Friday•Homeworks will be less mathematically intense starting with the second half of HW7•Details on Project 2 demo and Mini-Midterm 3 details on Monday3EE40 Summer 2010HugMidterm 2•I can show you your midterm 2 grade, but problem 5 needs regrading [most people will get 3 to 6 more points]•At the moment, mean is 102 and standard deviation is 24•First midterm was mean 103, standard deviation 20•Some oochness will happen here4EE40 Summer 2010HugLogic Gates and Static Discipline•(On the board before we started)5EE40 Summer 2010HugiClicker Warmup•We’re going to have a ton of iClicker questions today•A quick warmup. Have you played Starcraft 2?A. YesB. NoC. Starwhat?6EE40 Summer 2010HugField Effect Transistor+–C- - - - - - - - - - - - - (Drain)(Source)(Gate)+-7EE40 Summer 2010HugField Effect Transistor+–C•When the channel is present, then effective resistance of P region dramatically decreases•Thus:–When C is “off”, switch is open–When C is “on”, switch is closed- - - - - - - - - - - - - (Drain)(Source)(Gate)+-8EE40 Summer 2010HugField Effect Transistor+–C•If we apply a positive voltage to the plus side–Current begins to flow from + to ––Channel on the + side is weakened•If we applied a different positive voltage to both sides? - - - - - - (Drain)(Source)(Gate)+-+-9EE40 Summer 2010HugField Effect Transistor Summary•“Switchiness” is due to a controlling voltage which induces a channel of free electrons•Extremely easy to make in unbelievable numbers•Ubiquitous in all computational technology everywhere10EE40 Summer 2010HugDiscussion Today•In discussion today, we’ll go over the physics of MOSFETs for those of you who are curious•Time permitting, we’ll discuss at a future date in class as well (so yeah, it will be slightly redundant)11EE40 Summer 2010HugMOSFET Model•Schematically, we represent the MOSFET as a three terminal device•Can represent all the voltages and currents between terminals as shown to the right12EE40 Summer 2010HugMOSFET Model+–C(Drain)(Source)(Gate)13EE40 Summer 2010HugS Model of the MOSFET14EE40 Summer 2010HugBuilding a NAND gate using MOSFETsABC15EE40 Summer 2010HugMOSFET modeling•MOSFET models vary greatly in complexity•For example, an “ON” MOSFET has some effective resistance (not an ideal switch)•We will progressively refine our model of the MOSFET–Will add capacitance later today–If we have time in the next 2 weeks, we will also talk about using MOSFETs as analog amplifiers which will necessitate an even better model16EE40 Summer 2010HugSR Model of the MOSFET[Has nothing to do with SR flip-flop]17EE40 Summer 2010HugNAND with the SR ModelQ218EE40 Summer 2010HugNAND with the SR ModelQ319EE40 Summer 2010HugNAND with the SR ModelQ420EE40 Summer 2010HugAnother SR Model ExampleQ521EE40 Summer 2010HugAnother SR Model ExampleQ622EE40 Summer 2010HugThe power of digital circuits•At each stage, circuit restores the signal•Can think of each MOSFET as diverting the 5V or 0V power supply into the next gate•Tolerant to noise and manufacturing error0.48V5V0.45V23EE40 Summer 2010HugThe power of digital circuits•How much noise could we tolerate on the input of the 2nd gate?•On the input of the 3rd gate?0.48V5V0.45VOUTAG1G224EE40 Summer 2010HugThe power of digital circuits (literally)•Like all circuits, digital circuits consume power•Amount of power will be dependent on state of our MOSFET switches25EE40 Summer 2010HugPower ExampleQ726EE40 Summer 2010HugPower Example•In general, power consumption will depend on which inputs are high and which are low•“Worst case analysis” is when we pick the set of inputs which consumes the most power27EE40 Summer 2010HugStatic Power•Using only NMOS to implement our gates will result in a gate which constantly eats up power–If you wire such a gate up on a breadboard, it will hum along using power all day•Later today, we will see a technique called CMOS to avoid this static power dissipation•But first, let’s discuss delay28EE40 Summer 2010HugThe SRC Model of an NMOS Transistor•So far, our NMOS implementation of logic gates allow for instantaneous switching•In real life, of course, an NMOS implementation will take some non-zero time to switchSimulation by Wade BarnesGreen: Inverter InputRed: Inverter Output29EE40 Summer 2010HugThe SRC Model30EE40 Summer 2010HugThe SRC Model31EE40 Summer 2010HugSRC Model32EE40 Summer 2010HugSRC Model of our 2 Inverters•We decide to ignore the function of the gate on the right, keeping it in mind only because we know we’ll have to charge it33EE40 Summer 2010HugAnalysis of SRC ModelQ834EE40 Summer 2010HugAnalysis of SRC ModelQ935EE40 Summer 2010HugAnalysis of SRC ModelQ1036EE40 Summer 2010HugTiming Analysis of the SRC modelQ1137EE40 Summer 2010HugTiming Analysis of the SRC model38EE40 Summer 2010HugTiming Analysis of the SRC model39EE40 Summer 2010HugFall Time40EE40 Summer 2010HugTiming Analysis of the SRC model•How do we find the Rise Time?•Have to replace by new equivalent circuit where:–Capacitor is initially discharged (0.476 V)–Switch is open41EE40
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