EE40 Lecture 15 Josh Hug 7 30 2010 EE40 Summer 2010 Hug 1 Logistics HW7 due Tuesday HW8 will be due next Friday Homeworks will be less mathematically intense starting with the second half of HW7 Details on Project 2 demo and MiniMidterm 3 details on Monday EE40 Summer 2010 Hug 2 Midterm 2 I can show you your midterm 2 grade but problem 5 needs regrading most people will get 3 to 6 more points At the moment mean is 102 and standard deviation is 24 First midterm was mean 103 standard deviation 20 Some oochness will happen here EE40 Summer 2010 Hug 3 Logic Gates and Static Discipline On the board before we started EE40 Summer 2010 Hug 4 iClicker Warmup We re going to have a ton of iClicker questions today A quick warmup Have you played Starcraft 2 A Yes B No C Starwhat EE40 Summer 2010 Hug 5 Field Effect Transistor Drain Gate C Source EE40 Summer 2010 Hug 6 Field Effect Transistor Drain Gate C Source When the channel is present then effective resistance of P region dramatically decreases Thus When C is off switch is open When C is on switch is closed EE40 Summer 2010 Hug 7 Field Effect Transistor Drain Gate C Source If we apply a positive voltage to the plus side Current begins to flow from to Channel on the side is weakened If we applied a different positive voltage to both sides EE40 Summer 2010 Hug 8 Field Effect Transistor Summary Switchiness is due to a controlling voltage which induces a channel of free electrons Extremely easy to make in unbelievable numbers Ubiquitous in all computational technology everywhere EE40 Summer 2010 Hug 9 Discussion Today In discussion today we ll go over the physics of MOSFETs for those of you who are curious Time permitting we ll discuss at a future date in class as well so yeah it will be slightly redundant EE40 Summer 2010 Hug 10 MOSFET Model Schematically we represent the MOSFET as a three terminal device Can represent all the voltages and currents between terminals as shown to the right EE40 Summer 2010 Hug 11 MOSFET Model C Drain EE40 Summer 2010 Gate Source Hug 12 S Model of the MOSFET EE40 Summer 2010 Hug 13 Building a NAND gate using MOSFETs A C B EE40 Summer 2010 Hug 14 MOSFET modeling MOSFET models vary greatly in complexity For example an ON MOSFET has some effective resistance not an ideal switch We will progressively refine our model of the MOSFET Will add capacitance later today If we have time in the next 2 weeks we will also talk about using MOSFETs as analog amplifiers which will necessitate an even better model EE40 Summer 2010 Hug 15 SR Model of the MOSFET EE40 Summer 2010 Has nothing to do with SR flip flop Hug 16 NAND with the SR Model EE40 Summer 2010 Q2 Hug 17 NAND with the SR Model EE40 Summer 2010 Q3 Hug 18 NAND with the SR Model EE40 Summer 2010 Q4 Hug 19 Another SR Model Example EE40 Summer 2010 Q5 Hug 20 Another SR Model Example EE40 Summer 2010 Q6 Hug 21 The power of digital circuits At each stage circuit restores the signal Can think of each MOSFET as diverting the 5V or 0V power supply into the next gate Tolerant to noise and manufacturing error EE40 Summer 2010 0 48V 5V 0 45V Hug 22 The power of digital circuits How much noise could we tolerate on the input of the 2nd gate On the input of the 3rd gate A EE40 Summer 2010 G1 G2 0 48V 5V 0 45V OUT Hug 23 The power of digital circuits literally Like all circuits digital circuits consume power Amount of power will be dependent on state of our MOSFET switches EE40 Summer 2010 Hug 24 Power Example EE40 Summer 2010 Q7 Hug 25 Power Example In general power consumption will depend on which inputs are high and which are low Worst case analysis is when we pick the set of inputs which consumes the most power EE40 Summer 2010 Hug 26 Static Power Using only NMOS to implement our gates will result in a gate which constantly eats up power If you wire such a gate up on a breadboard it will hum along using power all day Later today we will see a technique called CMOS to avoid this static power dissipation But first let s discuss delay EE40 Summer 2010 Hug 27 The SRC Model of an NMOS Transistor So far our NMOS implementation of logic gates allow for instantaneous switching In real life of course an NMOS implementation will take some non zero time to switch Green Inverter Input Red Inverter Output EE40 Summer 2010 Simulation by Wade Barnes Hug 28 The SRC Model EE40 Summer 2010 Hug 29 The SRC Model EE40 Summer 2010 Hug 30 SRC Model EE40 Summer 2010 Hug 31 SRC Model of our 2 Inverters We decide to ignore the function of the gate on the right keeping it in mind only because we know we ll have to charge it EE40 Summer 2010 Hug 32 Analysis of SRC Model EE40 Summer 2010 Q8 Hug 33 Analysis of SRC Model EE40 Summer 2010 Q9 Hug 34 Analysis of SRC Model EE40 Summer 2010 Q10 Hug 35 Timing Analysis of the SRC model EE40 Summer 2010 Q11 Hug 36 Timing Analysis of the SRC model EE40 Summer 2010 Hug 37 Timing Analysis of the SRC model EE40 Summer 2010 Hug 38 Fall Time EE40 Summer 2010 Hug 39 Timing Analysis of the SRC model How do we find the Rise Time Have to replace by new equivalent circuit where Capacitor is initially discharged 0 476 V Switch is open EE40 Summer 2010 Hug 40 Timing Analysis of the SRC model EE40 Summer 2010 Hug 41 Timing Analysis of the SRC model EE40 Summer 2010 Hug 42 Timing Analysis of the SRC model EE40 Summer 2010 Hug 43 Propagation Delay EE40 Summer 2010 Hug 44 Reminder of Where We Started Wanted to study gate delay of So used SRC model Which implements A EE40 Summer 2010 G1 OUT Giving delay of LEFT gate Hug 45 Using Propagation Delays EE40 Summer 2010 01 10 01 A G1 OUT Hug 46 Propagation Delays A EE40 Summer 2010 G1 OUT Hug 47 Bonus Question for CS61C Veterans A EE40 Summer 2010 G1 OUT Hug 48 This is where we stopped EE40 Summer 2010 Hug 49 Power in the SRC Model Static power in the SRC Model is exactly as SR Model compare We re also interested in the dynamic power while capacitance is charging Algebra is a bit involved We ll outline the concept Book has a very thorough treatment in sections 11 1 through 11 3 EE40 Summer 2010 Hug 50 Dynamic Power in NMOS Circuits When our inverter is going from low to high we have the circuit on the left In general looks like circuit on the right EE40 Summer 2010 Hug 51 Dynamic Power in NMOS Circuits When our inverter is going from high to low we have the circuit on …
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