Lecture 24 OUTLINE The common source CS amplifier load line analysis DC bias circuit example small signal analysis of CS amplifier Reference Reading Howe Sodini Chapter 8 1 8 3 Hambley posted online Chapter 12 2 12 5 EECS40 Fall 2003 Lecture 24 Slide 1 Prof King Notation Subscript convention Lecture 2 Slide 11 VDS VD VS VGS VG VS etc Double subscripts denote DC sources Lecture 23 Slide 7 VDD VCC ISS etc To distinguish between DC and AC components of an electrical quantity the following convention is used DC quantity upper case letter with upper case subscript ID VDS etc AC quantity lower case letter with lower case subscript id vds etc Total DC AC quantity lower case letter with upper case subscript iD vDS etc EECS40 Fall 2003 Lecture 24 Slide 2 Prof King 1 P Channel MOSFET Example In a digital circuit a p channel MOSFET in the ON state is typically used to charge a capacitor connected to its drain terminal gate voltage VG 0 V source voltage VS VDD power supply voltage drain voltage VD initially at 0 V charging toward VDD VDD Req 0V iD Cload 3 VDD 5 1 pVDD 4 I DSATp 6 I DSAT EECS40 Fall 2003 k p W VDD VTp 2 L Lecture 24 Slide 3 2 Prof King Common Source CS Amplifier The input voltage vs causes vGS to vary with time which in turn causes iD to vary The changing voltage drop across RD causes an amplified and inverted version of the input signal to appear at the drain terminal VDD RD iD VBIAS EECS40 Fall 2003 vs vIN vGS vOUT vDS Lecture 24 Slide 4 Prof King 2 Load Line Analysis of CS Amplifier The operating point of the circuit can be determined by finding the intersection of the appropriate MOSFET iD vs vDS characteristic and the load line iD mA load line equation VDD RD iD vDS vGS V vDS V EECS40 Fall 2003 Lecture 24 Slide 5 Prof King Voltage Transfer Function vOUT vIN Goal Operate the amplifier in the high gain region so that small changes in vIN result in large changes in vOUT 1 transistor biased in cutoff region 2 vIN VT transistor biased in saturation region 3 transistor biased in saturation region 4 transistor biased in resistive or triode region EECS40 Fall 2003 Lecture 24 Slide 6 Prof King 3 Quiescent Operating Point The operating point of the amplifier for zero input signal vs 0 is often referred to as the quiescent operating point or Q point The Q point should be chosen so that the output voltage is approximately centered between VDD and 0 V vs varies the input voltage around the Q point Note The relationship between vOUT and vIN is not linear this results in a distorted output voltage signal If the input signal amplitude is very small however we can have amplification with negligible distortion EECS40 Fall 2003 Lecture 24 Slide 7 Prof King Bias Circuit Example VDD RD R1 R2 EECS40 Fall 2003 Lecture 24 Slide 8 Prof King 4 Rules for Small Signal Analysis A DC supply voltage source acts as a short circuit Even if AC current flows through the DC voltage source the AC voltage across it is zero A DC supply current source acts as an open circuit Even if AC voltage is applied across the current source the AC current through it is zero EECS40 Fall 2003 Lecture 24 Slide 9 Prof King Small Signal Equivalent Circuit G vin D R1 R2 vgs gmvgs ro RD vout S S vout g m v gs ro RD voltage gain EECS40 Fall 2003 Av vout g m ro RD vin Lecture 24 Slide 10 Prof King 5
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