Lecture 15 with Prof Sanders ANNOUNCEMENTS Prof King s office hour today is cancelled Farhana s office hours this week are cancelled HW 5 will be available on Friday 10 3 due 10 10 Pick up graded midterms in discussion sections OUTLINE Transient response of 1st order circuits Application modeling of digital logic gate Reading Chapter 7 3 7 5 EECS40 Fall 2003 Lecture 15 Slide 1 Prof King Transient Response of 1st Order Circuits In Lectures 13 and 14 we saw that the currents and voltages in RL and RC circuits decay exponentially with time with a characteristic time constant when an applied current or voltage is suddenly removed In general when an applied current or voltage suddenly changes the voltages and currents in an RL or RC circuit will change exponentially with time from their initial values to their final values with the characteristic time constant x t x f x t0 x f e t t0 where x t is the circuit variable voltage or current xf is the final value of the circuit variable t0 is the time at which the change occurs EECS40 Fall 2003 Lecture 15 Slide 2 Prof King 1 Procedure for Finding Transient Response 1 Identify the variable of interest For RL circuits it is usually the inductor current iL t For RC circuits it is usually the capacitor voltage vc t 2 Determine the initial value at t t0 of the variable Recall that iL t and vc t are continuous variables iL t0 iL t0 and vc t0 vc t0 Assuming that the circuit reached steady state before t0 use the fact that an inductor behaves like a short circuit in steady state or that a capacitor behaves like an open circuit in steady state EECS40 Fall 2003 Lecture 15 Slide 3 Prof King Procedure cont d 3 Calculate the final value of the variable its value as t Again make use of the fact that an inductor behaves like a short circuit in steady state t or that a capacitor behaves like an open circuit in steady state t 4 Calculate the time constant for the circuit L R for an RL circuit where R is the Th venin equivalent resistance seen by the inductor RC for an RC circuit where R is the Th venin equivalent resistance seen by the capacitor EECS40 Fall 2003 Lecture 15 Slide 4 Prof King 2 Example RL Transient Analysis Find the current i t and the voltage v t t 0 R 50 i Vs 100 V v L 0 1 H 1 First consider the inductor current i 2 Before switch is closed i 0 immediately after switch is closed i 0 3 A long time after the switch is closed i Vs R 2 A 4 Time constant L R 0 1 H 50 0 002 seconds i t 2 0 2 e t 0 0 002 2 2e 500t Amperes EECS40 Fall 2003 Lecture 15 Slide 5 t 0 Prof King R 50 i Vs 100 V v L 0 1 H Now solve for v t for t 0 From KVL EECS40 Fall 2003 v t 100 iR 100 2 2e 500t 50 Lecture 15 Slide 6 Prof King 3 Example RC Transient Analysis Find the current i t and the voltage v t R1 10 k Vs 5 V t 0 i v R2 10 k C 1 F 1 First consider the capacitor voltage v 2 Before switch is moved v 0 immediately after switch is moved v 0 3 A long time after the switch is moved v Vs 5 V 4 Time constant R1C 104 10 6 F 0 01 seconds v t 5 0 5 e t 0 0 01 5 5e 100t Volts EECS40 Fall 2003 Lecture 15 Slide 7 R1 10 k Vs 5 V R2 10 k Prof King t 0 i v C 1 F Now solve for i t for t 0 Vs v t 5 5 5e 100t From Ohm s Law i t R1 10 4 EECS40 Fall 2003 Lecture 15 Slide 8 Prof King 4 Application to Digital Integrated Circuits ICs When we perform a sequence of computations using a digital circuit we switch the input voltages between logic 0 e g 0 Volts and logic 1 e g 5 Volts The output of the digital circuit changes between logic 0 and logic 1 as computations are performed EECS40 Fall 2003 Lecture 15 Slide 9 Prof King Digital Signals We send beautiful pulses in voltage We compute with pulses But we receive lousy looking pulses at the output voltage time time Capacitor charging effects are responsible Every node in a real circuit has capacitance it s the charging of these capacitances that limits circuit performance speed EECS40 Fall 2003 Lecture 15 Slide 10 Prof King 5 Circuit Model for a Logic Gate Recall from Lecture 1 that electronic building blocks referred to as logic gates are used to implement logical functions NAND NOR NOT in digital ICs Any logical function can be implemented using these gates A logic gate can be modeled as a simple RC circuit R Vin t Vout C switches between low logic 0 and high logic 1 voltage states EECS40 Fall 2003 Lecture 15 Slide 11 Prof King Logic Level Transitions Transition from 0 to 1 capacitor charging Vout t Vhigh 1 e t RC Transition from 1 to 0 capacitor discharging Vout t Vhigh e t RC Vout Vout Vhigh Vhigh 0 63Vhigh 0 37Vhigh 0 RC time 0 RC time Vhigh is the logic 1 voltage level EECS40 Fall 2003 Lecture 15 Slide 12 Prof King 6 Sequential Switching Vin What if we step up the input 0 time 0 Vin wait for the output to respond Vout 0 time then bring the input back down Vin 0 Vout 0 EECS40 Fall 2003 Lecture 15 Slide 13 time 0 Prof King Pulse Distortion R Vin t The input voltage pulse width must be long enough otherwise the output pulse is distorted Vout C We need to wait for the output to reach a recognizable logic level before changing the input again Pulse width RC Pulse width 10RC Vout Vout 6 5 4 3 2 1 0 0 1 2 Time 3 EECS40 Fall 2003 4 5 6 5 4 3 2 1 0 Vout Pulse width 0 1RC 6 5 4 3 2 1 0 0 1 2 Time 3 4 Lecture 15 Slide 14 5 0 5 10 Time 15 20 25 Prof King 7 Example Suppose a voltage pulse of width 5 s and height 4 V is applied to the input of this circuit beginning at t 0 R Vin Vout C R 2 5 k C 1 nF RC 2 5 s First Vout will increase exponentially toward 4 V When Vin goes back down Vout will decrease exponentially back down to 0 V What is the peak value of Vout The output increases for 5 s or 2 time constants It reaches 1 e 2 or 86 of the final value 0 86 x 4 V 3 44 V is the peak value EECS40 …
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