EE40 Lec 20 MOS Circuits Reading Chap 12 of Hambley Supplement reading on MOS Circuits http www inst eecs berkeley edu ee40 fa09 handouts EE40 MOS Circuit pdf EE40 Fall 2009 Slide 1 Prof Cheung OUTLINE Bias circuits Small signal equivalent circuits Examples Common source amplifier Source follower Common gate amplifier Digital Gates CMOS EE40 Fall 2009 Slide 2 Prof Cheung Bias Circuits Use load line to find Quiescent operating point Remember no current flow through the gate Fixed plus Self Bias CKT VDD VDD RD RD R1 VG vin R2 EE40 Fall 2009 Slide 3 RS Prof Cheung Steps for MOSFET Circuit Analysis 1 Look at DC case to find Q point Use load line technique All capacitors are open circuit Inductors are short circuit Determine Q point get gm and rd for small signal AC model 2 AC Small signal analysis DC source is ac ground because there is no AC signal variation All capacitors are approximated as short circuit unless otherwise specified EE40 Fall 2009 Slide 4 Prof Cheung Example Common Source Amplifier VDD RD R1 C v t EE40 Fall 2009 vin RL VG R2 Slide 5 C RS vo C Prof Cheung Step 1 find Q point VG VDD R2 R1 R2 VDD Not connected for DC component VGS VG I D RS VDD I D RD RS VDS RD C R1 C v t vin VG R2 VDS RS RL vo C Not connected for DC component EE40 Fall 2009 Slide 6 Prof Cheung Load line to determine Q Point by graphical method Loadline to determine VGSQ VG VGS ID RS ID V DD V DS R0 RS ID VGSQ VG VGS RS Loadline to determine VDSQ ID VDD VDS R 0 RS From load lines we get ID and hence gm and rd EE40 Fall 2009 Slide 7 Prof Cheung Load line to determine Q Point by analytical method Solve VGSQ assume saturation region first I DQ VG VGSQ RS I DQ K VGSQ V t 2 IDQ is known then solve VDSQ VDD I DQ R D R S VDSQ Check VDSQ value is consistent with saturation region i e VDS VGSQ Vt From load lines we get ID and hence gm and rd EE40 Fall 2009 Slide 8 Prof Cheung Determination of gm and rd graphically Example Q point is known to be VGS 2 5V VDS 6V i D 2 9 2 3 mA 1 0 05 10 3 Siemens rd vDS 14 2 V or rd 20k EE40 Fall 2009 Slide 9 Prof Cheung Determination of gm and rd by Analytical Models In Saturation Region i D K v GS Vt 2 i D gm 2K v GS Vt 2 K i DQ v GS KP W 2 L channel mod ulation factor K i D 1 rd i DQ v DS In Triode Region i D K 2 v GS Vt v DS v 2 DS gm i D 2Kv DSQ v GS 1 rd i D K 2 v GSQ Vt 2 v DSQ v DS EE40 Fall 2009 Slide 10 Prof Cheung Small Signal Model Inverting vg vin vs 0 vgs vin For output impedance Rout 1 Turn off all independent sources 2 Take away load impedance RL RL RD vo g m vgs RL RD Av vo RR gm L D vin RL RD vin 0 vgs 0 g m vgs 0 vin R1 R2 Rin iin R1 R2 EE40 Fall 2009 Rout Slide 11 rd RD rd RD Prof Cheung Example Source Follower VDD R1 C v t EE40 Fall 2009 vin VG R2 Slide 12 C RS RL vo Prof Cheung Step 1 find Q point VG VDD R2 R1 R2 VDD VGS VG I D RS VDD I D RS VDS R1 C v t EE40 Fall 2009 vin VG R2 Slide 13 C RS RL vo Prof Cheung Small Signal Model Non inverting Voltage Gain 1 Rin high Current gain can be high RL 1 rd 1 RS 1 RL 1 vgs vin vo vo g m vgs RL vin vgs 1 g m RL vo g m RL Av vin 1 g m RL v RR Rin in 1 2 iin R1 R2 EE40 Fall 2009 For output impedance Rout 1 Turn off all independent sources 2 Take away RL 3 Add Vx and find ix vx vs vg 0 vgs vx Rs Rout rd Rs v ix x g m vx vx Rs 1 g m rd Rs Rs 1 g m rd 1 Rs 1 Slide 14 Rout is small Prof Cheung Example Common Gate Amplifier VDD RD C RL VG v t vo C vin RS VSS EE40 Fall 2009 Slide 15 Prof Cheung Step 1 find Q point VDD VGS 0 I D RS VSS VDD VSS I D RD RS VDS RD C RL VG v t vo C vin RS VSS EE40 Fall 2009 Slide 16 Prof Cheung Load line The only difference in all three circuits are the intercepts at the axes Again from load lines we get ID and hence gm and rd EE40 Fall 2009 Slide 17 Prof Cheung Small Signal Model Non inverting RL 1 RL 1 RD 1 vgs vin vo g m vgs RL Av vo g m RL vin iin g m vgs vgs Rs For output impedance Rout 1 Turn off all independent sources 2 Take away RL 3 Add Vx and find ix RRs R R Rs vx ix g m vgs RD vgs g m vgs R but g m R 1 vgs 0 v 1 Rin in iin g m Rs 1 EE40 Fall 2009 Rout RD Slide 18 Prof Cheung Logic Gates Pull Up and Pull Down PMOS or Resistor NMOS or Resistor EE40 Fall 2009 Slide 19 Prof Cheung Inverter NOT Gate Vin Vout Ideal Transfer Characteristics Vout V 2 EE40 Fall 2009 Slide 20 V Vin Prof Cheung NMOS Inverter Resistor Pull Up VDD Circuit Voltage Transfer Characteristic vOUT RD iD A iD vIN VDD F vDS vOUT vIN VDD 0 VT VDD VDD RD increasing vGS vIN VT 0 EE40 Fall 2009 vGS vin VT Slide 21 VDD vDS A F 0 1 1 0 Prof Cheung vIN NMOS NAND Gate Output is low only if both inputs are high VDD RD F A Truth Table A 0 0 1 1 B EE40 Fall 2009 Slide 22 B 0 1 0 1 Prof Cheung F 1 1 1 0 NMOS NOR Gate Output is low if either input is high VDD RD F A B Truth Table A 0 0 1 1 EE40 Fall 2009 Slide 23 B 0 1 0 1 Prof Cheung F 1 0 0 0 Disadvantages of NMOS Logic Gates Large values of RD are required in order to achieve a low value of VLOW keep power consumption low Large resistors are needed but these take up a lot of space EE40 Fall 2009 Slide 24 Prof Cheung CMOS Inverter Intuitive Perspective SWITCH MODELS CIRCUIT VDD G VDD VDD S Rp D VOUT VIN VOUT D G S Low static power consumption since one MOSFET is always off in steady state EE40 Fall 2009 Rn …
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