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Berkeley ELENG 40 - MOS Circuits

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Slide 1EE40 Fall 2009 Prof. CheungEE40 Lec 20MOS CircuitsReading: Chap. 12 of HambleySupplement reading on MOS Circuitshttp://www.inst.eecs.berkeley.edu/~ee40/fa09/handouts/EE40_MOS_Circuit.pdfSlide 2EE40 Fall 2009 Prof. CheungOUTLINE–Bias circuits–Small-signal equivalent circuits –Examples:Common source amplifier Source follower Common gate amplifier–Digital Gates–CMOSSlide 3EE40 Fall 2009 Prof. CheungBias Circuits• Use load line to find Quiescent operating point.• Remember no current flow through the gate.VDDRDR1R2RSVDDRDVG+vinFixed-plus Self-Bias CKTSlide 4EE40 Fall 2009 Prof. CheungSteps for MOSFET Circuit Analysis• 1) Look at DC case to find Q point– Use load line technique– All capacitors are open circuit, Inductors are short circuit– Determine Q-point, get gm and rdfor small signal AC model• 2) AC Small signal analysis– DC source is ac ground (because there is no AC signal variation).– All capacitors are approximated as short circuit (unless otherwise specified).Slide 5EE40 Fall 2009 Prof. CheungExample: Common Source AmplifierVDDRDR1R2RSCCRL+-voC+-vin+-v(t)VGSlide 6EE40 Fall 2009 Prof. CheungStep 1: find Q pointVDDRDR1R2RSCCRL+-voC+-vin+-v(t)VGVDS212()GDDGS G D SDDDD S DSRVVRRVVIRVIRRV=+=−=++Not connectedfor DC componentNot connectedfor DC componentSlide 7EE40 Fall 2009 Prof. CheungLoad line to determine Q Point by graphical methodFrom load lines, we get ID Æ and hence gmand rdSGSGDRVVI−=Loadline to determine VGSQSGSGDRVVI−=S0DSDDDRRVVI+−=S0DSDDDRRVVI+−=Loadline to determine VDSQVGSQSlide 8EE40 Fall 2009 Prof. CheungLoad line to determine Q Point by analytical methodFrom load lines, we get ID Æ and hence gmand rd2tGSQDQSGSQGDQ)VV(KIRVVI−=−=Solve VGSQ assume saturation region firstIDQis known, then solve VDSQ DSQSDDQDDV)RR(IV++=Check VDSQvalue is consistent with saturation region ( i.e. VDS> VGSQ-Vt)Slide 9EE40 Fall 2009 Prof. CheungDetermination of gmand rdgraphicallyExample: Q point is known to be VGS=2.5V, VDS=6VΩ=•=−−=∆∆=−krorSiemensVmAvirdDSDd201005.0)214()3.29.2(13Slide 10EE40 Fall 2009 Prof. CheungDetermination of gmand rdby Analytical ModelsDQDSDdDQtGSGSDm2tGSDivir/1iK2)Vv(K2vig)Vv(Ki•λ=∂∂==−=∂∂=−=factorulationmodchannelLW2KPK=λ=In Saturation RegionIn Triode Region]v2)Vv(2[Kvir/1Kv2vig]vv)Vv(2[KiDSQtGSQDSDdDSQGSDmDS2DStGSD−−=∂∂==∂∂=−−=Slide 11EE40 Fall 2009 Prof. CheungSmall Signal Model1212,0()gin s gs inLDomgsLDoLDvmin L Dinininvvv v vRRvgvRRvRRAgvRRvRRRiRR==→==−+==−+==+For output impedance Rout:1. Turn off all independent sources.2. Take away load impedance RL0, 0, 0in gs m gsdDoutdDvv gvrRRrR== ==+InvertingSlide 12EE40 Fall 2009 Prof. CheungExample: Source FollowerVDDR1R2RSCRL+-voC+-vin+-v(t)VGSlide 13EE40 Fall 2009 Prof. CheungStep 1: find Q point212GDDGS G D SDD D S DSRVVRRVVIRVIRV=+=−=+VDDR1R2RSCRL+-voC+-vin+-v(t)VGSlide 14EE40 Fall 2009 Prof. CheungSmall Signal Model11112121(1 )1LdSLgs in oomgsLin gs m LomLvinmLinininRrRRvvvvgvRvv gRvgRAvgRvRRRiRR−−−′=++=−′=′=+′==′+==+For output impedance Rout:1. Turn off all independent sources.2. Take away RL3. Add Vxand find ix()111,0,,()1xsg gs xds xsxmxxsmdssoutmd svvv v vrR vRigvvRgrRRRgr R−−−===−′′==−−=++′=++Non-inverting, Voltage Gain <1RinhighCurrent gain can be highRoutis smallSlide 15EE40 Fall 2009 Prof. CheungExample: Common Gate AmplifierVDDRDRSCRL+-voC+-vin+-v(t)VG-VSSSlide 16EE40 Fall 2009 Prof. CheungStep 1: find Q pointVDDRDRSCRL+-voC+-vin+-v(t)VG-VSS0()GS D S SSDD SS D D S DSVIRVVVIRRV=− ++= + +Slide 17EE40 Fall 2009 Prof. CheungLoad lineThe only difference in all three circuits are the intercepts at the axes.Again from load lines, we get ID Æ and hence gmand rdSlide 18EE40 Fall 2009 Prof. CheungSmall Signal Model1111()1LLDgs inomgsLovmLingsin m gssininin m sRRRvvvgvRvAgRvvigvRvRigR−−−′=+=−′=−′===− +==+For output impedance Rout:1. Turn off all independent sources.2. Take away RL3. Add Vxand find ix,10ssxxmgsDgs m gs m gsout DRRRRRvigvRv g v R but g R vRR′=+=+′′=−≠∴==Non-invertingSlide 19EE40 Fall 2009 Prof. CheungLogic Gates : Pull-Up and Pull-DownPMOS or ResistorNMOS or ResistorSlide 20EE40 Fall 2009 Prof. CheungInverter = NOT GateVoutVinVinVoutVV/2Ideal Transfer CharacteristicsSlide 21EE40 Fall 2009 Prof. CheungVDD/RDVDDNMOS Inverter: Resistor Pull-UpvDSiD0vOUTvIN0VDDRD+vDS= vOUT–iD+vIN–VDDRD+vDS= vOUT–iD+vIN–Circuit:Voltage-Transfer CharacteristicVDDVTAF0110AFincreasingvGS= vIN> VTvGS= vin≤ VT vIN= VDDVDDSlide 22EE40 Fall 2009 Prof. CheungNMOS NAND Gate• Output is low only if both inputs are highVDDRDABFAB F00 101 110 111 0Truth TableSlide 23EE40 Fall 2009 Prof. CheungNMOS NOR Gate• Output is low if either input is highVDDRDABFAB F00 101 010 011 0Truth TableSlide 24EE40 Fall 2009 Prof. CheungDisadvantages of NMOS Logic Gates• Large values of RDare required in order to– achieve a low value of VLOW– keep power consumption lowÆ Large resistors are needed, but these take up a lot of space.Slide 25EE40 Fall 2009 Prof. CheungCMOS Inverter: Intuitive PerspectiveVDDRnVIN= VDDCIRCUITSWITCH MODELSVDDRpVIN= 0 VVOUTVOUTVOL= 0 VVOH= VDDLow static power consumption, sinceone MOSFET is always off in steady stateVDDVINVOUTSDGGSDSlide 26EE40 Fall 2009 Prof. CheungThe CMOS Inverter: Current FlowVINVOUTVDDVDD00N: offP: linN: linP: offN: linP: satN: satP: linN: satP: satABDECiiISDGGSDVDDVOUTVINSlide 27EE40 Fall 2009 Prof. CheungPower Dissipation: Direct-Path CurrentVDD-VTVTtimevIN:i:IpeakVDD00iSDGGSDVDDvOUTvINpeakDDscdpIVtE=Energy consumed per switching period:tscSlide 28EE40 Fall 2009 Prof. CheungCMOS NAND GateAB F00 101 110 111 0AFBA BVDDNotice that the pull-up network is related to the pull-down network by DeMorgan’sTheorem!NMOS, Pull-down PMOS, Pull-upSlide 29EE40 Fall 2009 Prof. CheungCMOS NOR GateAFBABVDDAB F00 101 010 011 0Notice that the pull-up network is related to the pull-down network by DeMorgan’sTheorem!NMOS, Pull-down PMOS, Pull-upSlide 30EE40 Fall 2009 Prof. CheungMultiple Input NOR GateSlide 31EE40 Fall 2009 Prof. CheungFeatures of CMOS Digital Circuits• The output is always connected to VDDor GNDin steady state→ Full logic swing; large noise margins→ Logic levels are not dependent upon the relative sizes of the devices (“ratioless”)• There is no direct path between VDDand GNDin steady state→ no static power


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Berkeley ELENG 40 - MOS Circuits

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