EE40 Lecture 10 Josh Hug 7 17 2010 EE40 Summer 2010 Hug 1 Logistics and Lab Reminder If you have not submitted a spec and want to do a custom Project 2 talk to me right after class HW4 due today at 5 HW5 due Tuesday at 2PM it will be short and up by 5 PM today As requested all reading assignments for next week will be posted tonight We expect you to understand lab concepts For example the Schmitt Trigger Do you know what they are and what they do EE40 Summer 2010 Hug 2 HW Clarification There are a bunch of hints on the bspace forums Zero state response and zero input response are terms that I haven t used in lecture but they re really easy and they re in the book Zero input response The response you get with f t 0 same as homogeneous solution Zero state response The response you get with y 0 0 complete response with initial condition equal to zero EE40 Summer 2010 Hug 3 To the board For LC and RLC circuits EE40 Summer 2010 Hug 4 RLC Circuits They are important but not so much for digital integrated circuit design They do play a role in the world of analog circuits but that s a bit specialized for us to spend a great deal of time Usually care more about frequency response than the actual shape of the response in time If you want to learn more about analog circuit design it is hard and probably awesome see EE EE40 Summer 2010 Hug 5 Let s step back a second Earlier this week I said capacitors are good for Storing energy Filtering Modeling unwanted capacitances in digital circuits We ve discussed the first case pretty heavily now and filtering will come in great detail next week For now let s talk about delay modeling EE40 Summer 2010 Hug 6 Application to Digital Integrated Circuits ICs When we perform a sequence of computations using a digital circuit we switch the input voltages between logic 0 e g 0 Volts and logic 1 e g 5 Volts The output of the digital circuit changes between logic 0 and logic 1 as computations are performed EE40 Summer 2010 Hug 7 Digital Signals We send beautiful pulses in voltage We compute with pulses But we receive lousy looking pulses at the output voltage time time Capacitor charging effects are responsible Every node in a real circuit has capacitance it s the charging of these capacitances that limits circuit performance speed EE40 Summer 2010 Hug 8 Circuit Model for a Logic Gate As we ll discuss in a couple of weeks electronic building blocks referred to as logic gates are used to implement logical functions NAND NOR NOT in digital ICs Any logical function can be implemented using these gates A logic gate can be modeled as a simple RC circuit R Vin t C Vout switches between low logic 0 and high logic 1 voltage states EE40 Summer 2010 Hug 9 Logic Level Transitions Transition from 0 to 1 capacitor charging Vout t Vhigh 1 e t RC Vout Transition from 1 to 0 capacitor discharging Vout t Vhigh e t RC Vout Vhigh Vhigh 0 63Vhigh 0 37Vhigh 0 RC time 0 time RC Vhigh is the logic 1 voltage level EE40 Summer 2010 Hug 10 Sequential Switching Vin What if we step up the input 0 time wait for the output to respond Vin 0 Vout 0 time then bring the input back down Vin 0 Vout 0 EE40 Summer 2010 0 time Hug 11 Pulse Distortion R Vin t Vout C We need to wait for the output to reach a recognizable logic level before changing the input again Pulse width RC Vout Vout 6 5 4 3 2 1 0 Pulse width 10RC 0 1 2 Time EE40 Summer 2010 3 4 5 6 5 4 3 2 1 0 Vout Pulse width 0 1RC 6 5 4 3 2 1 0 The input voltage pulse width must be long enough otherwise the output pulse doesn t make it 0 1 2 Time 3 4 5 0 5 10 Time 15 20 Hug 25 12 Example Suppose a voltage pulse of width 5 s and height 4 V is applied to the input of this circuit beginning at t 0 RC 2 5 s Vin R R 2 5 k C 1 nF Vout C First Vout will increase exponentially toward 4 V When Vin goes back down Vout will decrease exponentially back down to 0 V What is the peak value of Vout The output increases for 5 s or 2 time constants It reaches 1 e 2 or 86 of the final value 0 86 x 4 V 3 44 V is the peak value EE40 Summer 2010 Hug 13 4 3 5 3 2 5 2 1 5 1 0 5 00 Vout t EE40 Summer 2010 2 4 6 8 10 4 4e t 2 5 s for 0 t 5 s 3 44e t 5 s 2 5 s for t 5 s Hug 14 Parasitic Capacitances We ll discuss these parasitic capacitances in the context of digital integrated circuits right after midterm 2 EE40 Summer 2010 Hug 15 AC Inputs EE40 Summer 2010 Hug 16 Solving Circuits with AC Sources In principle we can use the MPHS to solve the circuit below Will finding the homogeneous solution be difficult EE40 Summer 2010 Hug 17 Solving Circuits with AC Sources Will finding the particular solution be difficult EE40 Summer 2010 Hug 18 Solving Circuits with AC Sources Will finding the particular solution be difficult EE40 Summer 2010 Hug 19 Phasors EE40 Summer 2010 Hug 20 Two Paths Using Impedances and Phasors Solving ODEs MPHS Limited Trigonometry Hell Particular Solution Connector Route EE40 Summer 2010 Solution Town Hug 21 Basic Idea and Derivation of Impedances EE40 Summer 2010 Hug 22 New Voltage Source Problem EE40 Summer 2010 Hug 23 New Voltage Source Problem EE40 Summer 2010 Hug 24 To Recap AC source made it hard to find particular solution So we just replaced the annoying source giving us This gave us the particular solution EE40 Summer 2010 Hug 25 The Inverse Superposition Trick Our complex exponential source is actually useful EE40 Summer 2010 Hug 26 Inverse Superposition Just find real part and we re done EE40 Summer 2010 Hug 27 Real Part of Expression Finding the real part of the expression is easy it just involves some old school math that you ve probably forgotten HW5 will have complex number exercises EE40 Summer 2010 Hug 28 Real Part of Expression What we have is basically the product of two complex numbers Let s convert the left one to polar form EE40 Summer 2010 Hug 29 Real Part of Expression EE40 Summer 2010 Hug 30 Real Part of Expression Thus particular solution forced response of original cosine source is just the real part EE40 Summer 2010 Hug 31 Wait That was easier What we just did was mostly a derivation Only have to do the hard math one time Sort of like intuitive method for …
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