1 Embedded Benchmark Suite2 Math-Intense Benchmark SuiteAppendix A Background InformationA.1 Processor Clock vs Instruction Cycle Clock ConsiderationsA.2 Compiler Information And Detailed ResultsAppendix B Benchmarking ApplicationsB.1 Benchmarking ApplicationsB.2 Benchmarking Application Source Code1 Embedded Benchmark Suite010002000300040005000600070008000M SP430FG4619 M SP430F149 PIC24FJ128GA PIC18F242 8051 H8/ 300H M axQ20 ARM 7TDM I(Thumb)HCS12 ATmega8MicrocontrollerCode size in bytesUnoptimizedOptimizedApplication ReportSLAA205B – June 2005 – Revised July 2006MSP430 Competitive BenchmarkingGreg Morton, Kripasagar Venkat ................................................................................. MSP430 ProductsABSTRACTThis application report contains the results from benchmarking the MSP430 againstmicrocontrollers from other vendors. IAR Embedded Workbench™ developmentplatform was used to build and execute, in simulation mode, a set of simple mathfunctions. These functions were executed on each microcontroller to benchmarkdifferent aspects of the microcontrollers' performance. In addition, both Dhrystone andWhetstone analyses have been included.This section has results for simple and less intense math functions. Figure 1 shows the total code size inbytes for each microcontroller with no optimization and with full optimization.Figure 1. Total Code Size for Embedded Benchmark SuiteAll trademarks are the property of their respective owners.SLAA205B – June 2005 – Revised July 2006 MSP430 Competitive Benchmarking 1Submit Documentation Feedbackwww.ti.com01000020000300004000050000600007000080000M SP430FG4619 M SP430F149 PIC24FJ128GA PIC18F242 8051 H8/ 300H M axQ20 ARM 7TDM I(Thumb)HCS12 ATmega8MicrocontrollerCyclesUnoptimizedOptimizedEmbedded Benchmark SuiteFigure 2 shows the total cycle count for each microcontroller with no optimization and with fulloptimization. Note that some architectures use an internal CPU clock divider. In these architectures, thetotal execution time for the code is the clock divider multiplied by the total instruction cycle count. Thisclock divider is not included in the total cycle count numbers presented here. See Appendix A.1 for moreinformation regarding CPU clock dividers.Figure 2. Total Instruction Cycles for Embedded Benchmark SuiteThe MSP430FG4619 differs in architecture from the MSP430F149 and has the MSP430X CPU. TheMSP430X CPU can address up to 1-MB address range without paging. In addition, the MSP430X CPUhas fewer interrupt overhead cycles and fewer instruction cycles, in some cases, than the MSP430 CPU.The MSP430X CPU is completely backward compatible with the MSP430 CPU. Code size and cyclecount values are shown in Appendix A .2 MSP430 Competitive Benchmarking SLAA205B – June 2005 – Revised July 2006Submit Documentation Feedbackwww.ti.comEmbedded Benchmark SuiteTable 1 shows the total code size and the total instruction counts for each microcontroller, normalizedagainst the MSP430FG4619, for the Embedded Benchmark Suite.Table 1. Normalized Results for Embedded Benchmark SuiteTOTAL CODE SIZE TOTAL INSTRUCTION CYCLE COUNTMICROCONTROLLERUNOPTIMIZED FULLY OPTIMIZED UNOPTIMIZED FULLY OPTIMIZEDMSP430FG4619 1.00 1.00 1.00 1.00MSP430F149 1.01 1.003 1.04 1.09PIC24FJ128GA 1.80 1.62 0.93 0.84PIC18F242 1.75 1.77 5.79 2.798051 2.53 2.33 5.64 3.08H8/300H 1.94 1.81 3.22 3.60MaxQ20 1.38 1.26 2.22 1.04ARM7TDMI 2.30 2.26 0.76 0.37HCS12 1.40 1.38 2.49 2.03ATmega8 1.49 1.46 1.97 1.27Appendix B includes the code names and a brief description of their functionality used for thisbenchmarking.SLAA205B – June 2005 – Revised July 2006 MSP430 Competitive Benchmarking 3Submit Documentation Feedbackwww.ti.com2 Math-Intense Benchmark Suite05001000150020002500M SP430FG4619 M SP430F149 PIC24FJ128GA PIC18F242 8051 H8/ 300H M axQ20 ARM 7TDM I HCS12 ATmega8MicrocontrollerCode size in bytesUnoptimizedOptimizedMath-Intense Benchmark SuiteIn order to exhibit the performance of each of the microcontrollers under intense math operations, thebenchmarking of a Finite Impulse Response (FIR) filter that requires multiply and accumulate (MAC) isincluded in this report. Also included are the results of the Dhrystone and Whetstone benchmarks. Codesize and cycle count values are shown in Appendix A .Figure 3 shows the code size for each microcontroller, with no optimization and full optimization, for theimplementation of an FIR filter.Figure 3. Code Size For FIR Filter Operation4 MSP430 Competitive Benchmarking SLAA205B – June 2005 – Revised July 2006Submit Documentation Feedbackwww.ti.com020000040000060000080000010000001200000MSP430F G 4619 MSP430F 149 PIC 24F J128G A PIC18F 242 8051 H8/300H MaxQ 20 A RM 7T D M I HC S12 AT Meg a 8M icro co ntrollerCyclesUn o ptim iz edO ptim iz edMath-Intense Benchmark SuiteFigure 4 shows the cycle count for each microcontroller, with no optimization and full optimization, for theimplementation of an FIR filter.Figure 4. Cycle Count For FIR Filter OperationTable 2 shows the total code size and the total instruction cycle count for each microcontroller, normalizedagainst the MSP430FG4619, for the FIR filter operation.Table 2. Normalized Results for FIR Filter OperationTOTAL INSTRUCTIONTOTAL CODE SIZECYCLE COUNTMICROCONTROLLERUNOPTIMIZED FULLY OPTIMIZED UNOPTIMIZED FULLY OPTIMIZEDMSP430FG4619 1.00 1.00 1.00 1.00MSP430F149 1.006 1.006 1.04 1.04PIC24FJ128GA 1.61 1.52 1.12 1.13PIC18F242 2.02 1.99 2.17 1.688051 2.08 2.04 2.92 2.97H8/300H 1.41 1.38 2.52 2.51MaxQ20 1.56 1.47 1.56 1.54ARM7TDMI 1.52 1.52 0.33 0.31HCS12 1.91 1.90 9.23 9.54ATmega8 1.33 1.35 3.23 3.25SLAA205B – June 2005 – Revised July 2006 MSP430 Competitive Benchmarking 5Submit Documentation Feedbackwww.ti.com0500100015002000250030003500M SP430FG4619 M SP430F149 PIC24FJ128GA 8051 H8/ 300H M axQ20 ARM 7TDM I HCS12 ATmega8MicrocontrollerCode size in bytesUnoptimizedOptimizedMath-Intense Benchmark SuiteThe Dhrystone benchmark gauges the performance of a microcontroller in handling pointers, structures,and strings. Figure 5 shows the code size for each microcontroller, with no optimization and fulloptimization, for the implementation of this code.Figure 5. Code Size In Bytes For Dhrystone Analysis6 MSP430 Competitive Benchmarking SLAA205B – June 2005 – Revised July 2006Submit Documentation Feedbackwww.ti.com0100000200000300000400000500000600000700000800000M SP430FG4619 M SP430F149 PIC24FJ128GA 8051 H8/ 300H M axQ20 ARM 7TDM I HCS12
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