Application Report SLAA205B June 2005 Revised July 2006 MSP430 Competitive Benchmarking Greg Morton Kripasagar Venkat MSP430 Products ABSTRACT This application report contains the results from benchmarking the MSP430 against microcontrollers from other vendors IAR Embedded Workbench development platform was used to build and execute in simulation mode a set of simple math functions These functions were executed on each microcontroller to benchmark different aspects of the microcontrollers performance In addition both Dhrystone and Whetstone analyses have been included 1 Embedded Benchmark Suite This section has results for simple and less intense math functions Figure 1 shows the total code size in bytes for each microcontroller with no optimization and with full optimization 8000 Unoptimized Optimized 7000 Code size in bytes 6000 5000 4000 3000 2000 1000 0 M SP430FG4619 M SP430F149 PIC24FJ128GA PIC18F242 8051 H8 300H M axQ20 ARM 7TDM I Thumb HCS12 ATmega8 Microcontroller Figure 1 Total Code Size for Embedded Benchmark Suite All trademarks are the property of their respective owners SLAA205B June 2005 Revised July 2006 Submit Documentation Feedback MSP430 Competitive Benchmarking 1 www ti com Embedded Benchmark Suite Figure 2 shows the total cycle count for each microcontroller with no optimization and with full optimization Note that some architectures use an internal CPU clock divider In these architectures the total execution time for the code is the clock divider multiplied by the total instruction cycle count This clock divider is not included in the total cycle count numbers presented here See Appendix A 1 for more information regarding CPU clock dividers 80000 Unoptimized Optimized 70000 60000 Cycles 50000 40000 30000 20000 10000 0 M SP430FG4619 M SP430F149 PIC24FJ128GA PIC18F242 8051 H8 300H M axQ20 ARM 7TDM I Thumb HCS12 ATmega8 Microcontroller Figure 2 Total Instruction Cycles for Embedded Benchmark Suite The MSP430FG4619 differs in architecture from the MSP430F149 and has the MSP430X CPU The MSP430X CPU can address up to 1 MB address range without paging In addition the MSP430X CPU has fewer interrupt overhead cycles and fewer instruction cycles in some cases than the MSP430 CPU The MSP430X CPU is completely backward compatible with the MSP430 CPU Code size and cycle count values are shown in Appendix A 2 MSP430 Competitive Benchmarking SLAA205B June 2005 Revised July 2006 Submit Documentation Feedback www ti com Embedded Benchmark Suite Table 1 shows the total code size and the total instruction counts for each microcontroller normalized against the MSP430FG4619 for the Embedded Benchmark Suite Table 1 Normalized Results for Embedded Benchmark Suite MICROCONTROLLER TOTAL CODE SIZE TOTAL INSTRUCTION CYCLE COUNT UNOPTIMIZED FULLY OPTIMIZED UNOPTIMIZED FULLY OPTIMIZED MSP430FG4619 1 00 1 00 1 00 1 00 MSP430F149 1 01 1 003 1 04 1 09 PIC24FJ128GA 1 80 1 62 0 93 0 84 PIC18F242 1 75 1 77 5 79 2 79 8051 2 53 2 33 5 64 3 08 H8 300H 1 94 1 81 3 22 3 60 MaxQ20 1 38 1 26 2 22 1 04 ARM7TDMI 2 30 2 26 0 76 0 37 HCS12 1 40 1 38 2 49 2 03 ATmega8 1 49 1 46 1 97 1 27 Appendix B includes the code names and a brief description of their functionality used for this benchmarking SLAA205B June 2005 Revised July 2006 Submit Documentation Feedback MSP430 Competitive Benchmarking 3 www ti com Math Intense Benchmark Suite 2 Math Intense Benchmark Suite In order to exhibit the performance of each of the microcontrollers under intense math operations the benchmarking of a Finite Impulse Response FIR filter that requires multiply and accumulate MAC is included in this report Also included are the results of the Dhrystone and Whetstone benchmarks Code size and cycle count values are shown in Appendix A Figure 3 shows the code size for each microcontroller with no optimization and full optimization for the implementation of an FIR filter 2500 Unoptimized Optimized Code size in bytes 2000 1500 1000 500 0 M SP430FG4619 M SP430F149 PIC24FJ128GA PIC18F242 8051 H8 300H M axQ20 ARM 7TDM I HCS12 ATmega8 Microcontroller Figure 3 Code Size For FIR Filter Operation 4 MSP430 Competitive Benchmarking SLAA205B June 2005 Revised July 2006 Submit Documentation Feedback www ti com Math Intense Benchmark Suite Figure 4 shows the cycle count for each microcontroller with no optimization and full optimization for the implementation of an FIR filter 1200000 U n o p t im iz e d O p t im iz e d 1000000 Cycles 800000 600000 400000 200000 0 M SP430F G 4619 M SP430F 149 P IC 2 4 F J 1 2 8 G A P IC 1 8 F 2 4 2 8051 H 8 3 0 0 H M axQ 20 A R M 7T D M I H C S12 A T M eg a 8 M ic ro c o n tro lle r Figure 4 Cycle Count For FIR Filter Operation Table 2 shows the total code size and the total instruction cycle count for each microcontroller normalized against the MSP430FG4619 for the FIR filter operation Table 2 Normalized Results for FIR Filter Operation TOTAL INSTRUCTION CYCLE COUNT TOTAL CODE SIZE MICROCONTROLLER UNOPTIMIZED FULLY OPTIMIZED UNOPTIMIZED FULLY OPTIMIZED MSP430FG4619 1 00 1 00 1 00 1 00 MSP430F149 1 006 1 006 1 04 1 04 PIC24FJ128GA 1 61 1 52 1 12 1 13 PIC18F242 2 02 1 99 2 17 1 68 8051 2 08 2 04 2 92 2 97 H8 300H 1 41 1 38 2 52 2 51 MaxQ20 1 56 1 47 1 56 1 54 ARM7TDMI 1 52 1 52 0 33 0 31 HCS12 1 91 1 90 9 23 9 54 ATmega8 1 33 1 35 3 23 3 25 SLAA205B June 2005 Revised July 2006 Submit Documentation Feedback MSP430 Competitive Benchmarking 5 www ti com Math Intense Benchmark Suite The Dhrystone benchmark gauges the performance of a microcontroller in handling pointers structures and strings Figure 5 shows the code size for each microcontroller with no optimization and full optimization for the implementation of this code 3500 Unoptimized Optimized 3000 Code size in bytes 2500 2000 1500 1000 500 0 M SP430FG4619 M SP430F149 PIC24FJ128GA 8051 H8 300H M axQ20 ARM 7TDM I HCS12 ATmega8 Microcontroller Figure 5 Code Size In Bytes For Dhrystone Analysis 6 MSP430 Competitive Benchmarking SLAA205B June 2005 Revised July 2006 Submit Documentation Feedback www ti com Math Intense Benchmark Suite Figure 6 shows the cycle count for each microcontroller with no optimization and full optimization for the Dhrystone analysis 800000 Unoptimized Optimized 700000 600000 Cycles 500000 400000 300000 200000 100000 0 M SP430FG4619 M SP430F149 PIC24FJ128GA 8051 H8 300H M axQ20 ARM 7TDM I HCS12 ATmega8 Microcontroller Figure 6 Cycle Count For Dhrystone Analysis Table 3 shows the total code size and the total instruction cycle count for each
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