EE40 Lecture 16 Josh Hug 8 02 2010 EE40 Summer 2010 Hug 1 Logistics HW7 due tomorrow HW8 will be due Friday Mini midterm 3 next Wednesday 80 160 points will be a take home set of design problems which will utilize techniques we ve covered in class Handed out Friday Due next Wednesday Other 80 160 will be an in class midterm covering HW7 and HW8 Final will include Friday and Monday lecture Design problems will provide practice EE40 Summer 2010 Hug 2 Project 2 Active filter lab and Booster lab due this week For Booster lab ignore circuit simulation though it may be instructive to try the Falstad simulator Project 2 due next Wednesday EE40 Summer 2010 Hug 3 Design Problems ALL WORK MUST BE DONE COMPLETELY SOLO Maximum allowed time will be 5 hours Will be written so that it can be completed in approximately 2 hours Allowed resources May use any textbook incl Google Books Anything posted on the EE40 website Only allowed websites are Google Books wikipedia and EE40 websites Not allowed to use other websites like facebook answers yahoo answers etc even if you are reading other people s responses When in doubt email me or text me We will be very serious about cheating on this EE40 Summer 2010 Hug 4 Example Design Problem Design a circuit which will sum three sinusoidal input voltages and attenuate any frequencies above 10 000 Hz by at least 20 dB EE40 Summer 2010 Hug 5 Project 2 For those of you who want to demo Project 2 we ll be doing demos in lab on Wednesday Either at 1 PM after mini midterm Or at 2 PM during usual lab period Opinions EE40 Summer 2010 Hug 6 Interactive Lecture Question Did you like the interactive worksheet intensive MOSFET lecture A Yes it was extremely useful and I highly prefer this type of lecture B Yes it was useful but the usual 1 way lecture is fine C No real opinion D Didn t like it E Hated it EE40 Summer 2010 Hug 7 MOSFET Model Schematically we represent the MOSFET as a three terminal device Can represent all the voltages and currents between terminals as shown to the right EE40 Summer 2010 Hug 8 MOSFET modeling MOSFET models vary greatly in complexity S Model Good for explaining MOSFETs to someone with no EE knowledge SR Model Includes effective resistance of a MOSFET Good for understanding how to choose pull up resistance SR Model Include gate capacitance Good for understanding dynamic power and gate delay EE40 Summer 2010 Hug 9 S Model of the MOSFET The simplest model basically says that the MOSFET is Open for Closed for EE40 Summer 2010 Hug 10 SR Model of the MOSFET 0 EE40 Summer 2010 Has nothing to do with SR flip flop Hug 11 The SRC Model The SRC Model is almost identical to the SR model except that each gate node has a capacitance Like SR model open when OFF and resistive when ON Note that now is non zero EE40 Summer 2010 Hug 12 The SRC Model Useful for modeling Gate delay Takes time to charge up Dynamic power EE40 Summer 2010 Hug 13 SRC Model Consider our familiar pair of inverters We re going to focus on the behavior of our left inverter Let s assume that both MOSFETs have a gate capacitance of or EE40 Summer 2010 5 9 5 k 5 11k Hug 14 SRC Model of our 2 Inverters 5 9 5 k 5 11k 5 9 5 k 1 1 We decide to ignore the function of the gate on the right keeping it in mind only because we know we ll have to charge it EE40 Summer 2010 Hug 15 Timing Analysis of the SRC model Since and then How long will it take for the next inverter in the chain to turn on 5 9 5 k 1 1 10 12 EE40 Summer 2010 1 1 9500 1 0 00 1 06 10 9 Hug 16 Timing Analysis of the SRC model So We call this the Fall Time gives time for to fall from 5V to 1V EE40 Summer 2010 5 9 5 k 1 1 1 1 Hug 17 Fall Time Gives 5 9 5 k 1 1 1 EE40 Summer 2010 1 Hug 18 Timing Analysis of the SRC model How do we find the Rise Time Have to replace by new equivalent circuit where Capacitor is initially discharged 0 476 V Switch is open EE40 Summer 2010 5 9 5 k 1 1 1 1 Hug 19 Timing Analysis of the SRC model How do we find the Rise Time Have to replace by new equivalent circuit where Capacitor is initially discharged 0 476 V Switch is open EE40 Summer 2010 5 9 5 k 1 1 1 Hug 20 Timing Analysis of the SRC model 5 9 5 k 1 1 1 EE40 Summer 2010 Hug 21 Timing Analysis of the SRC model 5 9 5 k 1 1 1 EE40 Summer 2010 Hug 22 Propagation Delay Rise and Fall Time are also called Propagation Delays Gives delay time between when the logical input changes and the logical output changes Book calls them and EE40 Summer 2010 Hug 23 Reminder of Where We Started Wanted to study gate delay of 5 11k 5 9 5 k So used SRC model 5 9 5 k 1 1 Which implements A EE40 Summer 2010 G1 OUT Giving delay of LEFT gate Hug 24 Propagation Delays In general is not equal to Thus we usually just take the maximum and call that the propagation delay of the gate Means that no matter what input you give the gate output will be correct within A EE40 Summer 2010 G1 OUT Hug 25 Propagation Delay Is our analysis still correct if we add more output gates No gate capacitance increases Takes 3 times as long OUT1 A ln 0 884 EE40 Summer 2010 G1 OUT2 OUT3 Hug 26 Power in the SRC Model Static power in the SRC Model is exactly as SR Model compare We re also interested in the dynamic power while capacitance is charging Algebra is a bit involved We ll outline the concept Book has a very thorough treatment in sections 11 1 through 11 3 EE40 Summer 2010 Hug 27 Dynamic Power in NMOS Circuits When our inverter is going from low to high we have the circuit on the left In general looks like circuit on the right 5 9 5 k 1 1 1 EE40 Summer 2010 Hug 28 Dynamic Power in NMOS Circuits When our inverter is going from high to low we have the circuit on the left In general looks like circuit on the right 5 9 5 k 1 1 1 EE40 Summer 2010 1 Hug 29 Dynamic Power Worst case is that inverter is driven by a sequence of 1s and 0s Circuit constantly switching behavior Gate capacitor constantly charging and discharging 0 Charges up towards 1 Discharges down towards EE40 Summer 2010 Hug 30 Problem Setup is 0 for some time Dissipates some energy 1 for some …
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