LAST HOMEWORK 8 Due Friday at 5PM 8 6 2010 1 For this problem no resistors please a Implement the function b Implement the function have an inverter at the end c Implement the function d Implement the function have an inverter at the end using NMOS only using NMOS only your answer should not as a CMOS circuit as a CMOS circuit your answer should not 2 Take your circuit from part 1 d Different combinations of inputs will result in different rise and fall times For this problem assume that your PMOS network is connected to 5V and your NMOS network is connected to 0V Assume that all resistances are equal and the only capacitance is the gate source capacitance a Give a combination of inputs which results in the longest fall time Is there more than one set of inputs that gives this same longest fall time b Assume that when your input you find in part a is applied that the initial voltage was 4 5V in other words it hadn t had time to increase all the way to 5V while it was rising If the target low voltage is 2 5V what is the fall time for your worst case input combination from part a give your answer in terms of and c Give a combination of inputs which results in the shortest rise time Is there more than one set of inputs which gives this same shortest rise time d Now assume the rise starts from 0 5V If the target high voltage is 2 5V what is the rise time for your best case input combination from part c again give your answer in terms of and 3 In the book and in class we studied the power consumption when a signal is changing much more slowly than the rise and fall time so the capacitor can charge completely Usually we don t want to wait so long since Valid 1 will take far less time to reach than In this problem we will look at power consumption for the case where the switching time is very close to the rise and fall time Take your circuit from part 1 d Imagine that A 0 B 0 and C is a square wave with period so low for then high for For this problem your PMOS network is connected to and your NMOS network is connected to a Draw the SRC equivalent circuit Hint Yes you only need to draw one resistor and one capacitor when C has just become high Is rising or falling i What is for assuming that C went high at and ii Using your answer to part i how low does get before C goes low again at iii If the target voltage is what is the fall time for C Your answer should be shorter than iv What is for the total power dissipated in the whole circuit Hint Your on NMOS transistor is the only component that will dissipate power v How much energy is dissipated in seconds How much energy is dissipated during the entire time that is high For this one you don t need to do any integration of part a iv there s a faster way b Now at C becomes low Redraw the circuit for the case when C is now low i What is you ll need your answer to part a i ii What is for yes you ll need your answer to part b i iii Using your answer to part ii how low does get before C goes high again at iv If the target voltage is what is rise fall time for C Your answer should be shorter than v What is for the total power dissipated in the whole circuit vi How much energy is dissipated in seconds How much energy is dissipated during the entire time that is low For this one you do need to integrate your answer to part b v c Given your answers to part a v and b vi what is the average power consumed by the circuit given that it is being driven by a square wave on the input C d If we change the clock frequency can we still use our answers to part a v and b vi to calculate the average power Why or why not e If we change the clock frequency so that and what is the average power consumed by the circuit Yes this is just a formula f Extra not for a grade Note that your answer to b iii gives the same answer at that your answer to a i gives for Draw 4 Consider a CMOS NAND gate driving a gate capacitance of a If the gate capacitance discharging time constant for the falling case is for a 2 input NAND gate what is b If we now use the same transistors that we used in part a what is the gate capacitance discharging constant for an N input NAND gate c What is the worst case gate capacitance charging time constant for the same Ninput NAND gate The best case 5 For this problem use the Voltage Source model assuming Do parts a through c OR problem 5 expert edition a What is b What is c What is if if if is 21V is 5V is 0V Problem 5 expert edition Plot as a function of Hint Assume both diodes are off then find the conditions for where this assumption is true Then repeat for the other three conditions This will tell you what the state of the diodes is for every and once you know this you can find for every 6 I took a green LED and connected it directly to a voltage source in lab Schematically this looks as follows Here is the voltage output by the HP H3631A Triple Output DC Power Supply is the resistance of the clips wire and voltage source is the current supplied by the source as reported by the HP E3631A I collected the following data where supply voltage is on the left current on the right 1V 1 mA 1 5V 1 mA 1 7V 1 mA 1 8V 0 001A 1 9V 0 006A 2V 2 1 2 2V 2 3V 2 4V 2 5V 2 6V 2 7V 2 8V 2 9V 3V 4V 5V 0 012A 0 017A 0 023A 0 03 0 037A 0 045A 0 052A 0 06A 0 068A 0 075A 0 083A 0 144A 0 163A In this problem you will attempt to find values for which the VSR model in the diode handout is accurate You may assume that the resistance of the wire and voltage source are negligible compared to the resistance of the diode i e is effectively zero so all voltage is dissipated across the diode a According to the VSR model what shape will the I V characteristic have if b Based on the data roughly how big must V be before the SRC model is accurate i e when does it gain the shape you saw from part a c Use the …
View Full Document
Unlocking...