Memories: RAM, ROM Advanced TestbenchesSources & Required ReadingSlide 3Generic RAM (1)Generic RAM (2)Generic ROM (1)Generic ROM (2)Generic ROM (3) – hexadecimal notationSlide 9Distributed RAMRAM 16x1 (1)RAM 16x1 (2)RAM 16x1 (3)RAM 16x8 (1)RAM 16x8 (2)RAM 16x8 (3)ROM 16x1 (1)ROM 16x1 (2)ROM 16x1 (3)std_logic vs. std_ulogicConversion std_ulogic_vector => integerSlide 22ConstantsConstants - featuresSlide 25Physical data typesTime values (physical literals) - ExamplesTIME valuesUnits of timeValues of the type TIMEArithmetic operations on values of the type TIMESlide 32Records – Examples (1)Records – Examples (2)Slide 35AssertAssert - syntaxAssert - ExamplesSlide 39Variable – Example (1)Variable – Example (2)Variables - featuresSlide 43Slide 44Testbench (1)Testbench (2)Testbench (3)Testbench (4)Testbench (5)Slide 50Design Under Test (1)Design Under Test (2)Test vector file (1)Test vector file (2)Slide 55Slide 56Slide 57Slide 58Slide 59Slide 60Testbench (6)Testbench (7)Hex formatECE 545 – Introduction to VHDL George Mason UniversityMemories: RAM, ROMAdvanced TestbenchesECE 545Lecture 7ECE 545 – Introduction to VHDL 2Sources & Required Reading•Volnei A. Pedroni, Circuit Design with VHDLChapter 9.10, Memory DesignChapter 7.1, ConstantChapter 3.6, RecordsChapter 11.6, Assert•Sundar Rajan, Essential VHDL: RTL Synthesis Done RightChapter 14, starting from “Design Verification”ECE 545 – Introduction to VHDL 3GenericMemoriesECE 545 – Introduction to VHDL 4Generic RAM (1)LIBRARY ieee;USE ieee.std_logic_1164.all;-------------------------------------------------------------------------------------------------ENTITY ram ISGENERIC (bits: INTEGER:=8; -- # of bits per word words: INTEGER := 16); -- # of words in the memoryPORT (wr_ena, clk: IN STD_LOGIC; addr: IN INTEGER RANGE 0 to words-1; data_in: IN STD_LOGIC_VECTOR(bits -1 downto 0);data_out: OUT STD_LOGIC_VECTOR(bits – 1 downto 0) );END ram;ECE 545 – Introduction to VHDL 5Generic RAM (2)ARCHITECTURE behavioral OF ram ISTYPE vector_array IS ARRAY (0 TO words-1) OFSTD_LOGIC_VECTOR(bits – 1 DOWNTO 0);SIGNAL memory: vector array;BEGINPROCESS(clk)BEGINIF(wr_ena=‘1’) THEN IF (clk’EVENT AND clk=‘1’) THEN memory(addr) <= data_in; END_IF; END IF;END PROCESS;data_out <= memory(addr);END ram;ECE 545 – Introduction to VHDL 6Generic ROM (1)LIBRARY ieee;USE ieee.std_logic_1164.all;-------------------------------------------------------------------------------------------------ENTITY rom ISGENERIC (bits: INTEGER:=8; -- # of bits per word words: INTEGER := 8); -- # of words in the memoryPORT ( addr: IN INTEGER RANGE 0 to words-1;data: OUT STD_LOGIC_VECTOR(bits – 1 downto 0) );END rom;ECE 545 – Introduction to VHDL 7Generic ROM (2)ARCHITECTURE behavioral OF rom ISTYPE vector_array IS ARRAY (0 TO words-1) OFSTD_LOGIC_VECTOR(bits – 1 DOWNTO 0);CONSTANT memory: vector_array := ("0000_0000", "0000_0010", "0000_0100", "0000_1000", "0001_0000", "0010_0000", "0100_0000", "1000_0000");BEGINdata <= memory(addr);END rom;ECE 545 – Introduction to VHDL 8Generic ROM (3) – hexadecimal notation ARCHITECTURE behavioral OF rom ISTYPE vector_array IS ARRAY (0 TO words-1) OFSTD_LOGIC_VECTOR(bits – 1 DOWNTO 0);CONSTANT memory: vector_array := (X"00", X"02", X"04", X"08", X"10", X"20", X"40", X"80");BEGINdata <= memory(addr);END rom;ECE 545 – Introduction to VHDL 9FPGAspecific memoriesECE 545 – Introduction to VHDL 10RAM16X1SODWEWCLKA0A1A2A3RAM32X1SODWEWCLKA0A1A2A3A4RAM16X2SO1D0WEWCLKA0A1A2A3D1O0==LUTLUTorLUTRAM16X1DSPODWEWCLKA0A1A2A3DPRA0 DPODPRA1DPRA2DPRA3orDistributed RAM•CLB LUT configurable as Distributed RAM•A LUT equals 16x1 RAM•Implements Single and Dual-Ports•Cascade LUTs to increase RAM size•Synchronous write•Synchronous/Asynchronous read•Accompanying flip-flops used for synchronous readECE 545 – Introduction to VHDL 11RAM 16x1 (1)library IEEE;use IEEE.STD_LOGIC_1164.all;library UNISIM;use UNISIM.all;entity RAM_16X1_DISTRIBUTED is port( CLK : in STD_LOGIC; WE : in STD_LOGIC; ADDR : in STD_LOGIC_VECTOR(3 downto 0); DATA_IN : in STD_LOGIC; DATA_OUT : out STD_LOGIC );end RAM_16X1_DISTRIBUTED;ECE 545 – Introduction to VHDL 12RAM 16x1 (2)architecture RAM_16X1_DISTRIBUTED_STRUCTURAL of RAM_16X1_DISTRIBUTED is-- part used by the synthesis tool, Synplify Pro, only; ignored during simulation attribute INIT : string; attribute INIT of RAM16X1_S_1: label is "0000";------------------------------------------------------------------------component ram16x1sgeneric(INIT : BIT_VECTOR(15 downto 0) := X"0000");port(O : out std_ulogic;A0 : in std_ulogic;A1 : in std_ulogic;A2 : in std_ulogic;A3 : in std_ulogic;D : in std_ulogic;WCLK : in std_ulogic;WE : in std_ulogic);end component;ECE 545 – Introduction to VHDL 13RAM 16x1 (3)begin RAM_16X1_S_1: ram16x1s generic map (INIT => X”0000")port map(O => DATA_OUT, A0 => ADDR(0), A1 => ADDR(1), A2 => ADDR(2), A3 => ADDR(3), D => DATA_IN, WCLK => CLK, WE => WE ); end RAM_16X1_DISTRIBUTED_STRUCTURAL;ECE 545 – Introduction to VHDL 14RAM 16x8 (1)library IEEE;use IEEE.STD_LOGIC_1164.all;library UNISIM;use UNISIM.all;entity RAM_16X8_DISTRIBUTED is port( CLK : in STD_LOGIC; WE : in STD_LOGIC; ADDR : in STD_LOGIC_VECTOR(3 downto 0); DATA_IN : in STD_LOGIC_VECTOR(7 downto 0); DATA_OUT : out STD_LOGIC_VECTOR(7 downto 0) );end RAM_16X8_DISTRIBUTED;ECE 545 – Introduction to VHDL 15RAM 16x8 (2)architecture RAM_16X8_DISTRIBUTED_STRUCTURAL of RAM_16X8_DISTRIBUTED is attribute INIT : string;attribute INIT of RAM16X1_S_1: label is "0000";component ram16x1sgeneric(INIT : BIT_VECTOR(15 downto 0) := X"0000");port(O : out std_ulogic;A0 : in std_ulogic;A1 : in std_ulogic;A2 : in std_ulogic;A3 : in std_ulogic;D : in std_ulogic;WCLK : in std_ulogic;WE : in std_ulogic);end component;ECE 545 – Introduction to VHDL 16RAM 16x8 (3)beginGENERATE_MEMORY:for I in 0 to 7 generateRAM_16X1_S_1: ram16x1s generic map (INIT => X"0000")port map (O => DATA_OUT(I), A0 => ADDR(0), A1 => ADDR(1), A2 => ADDR(2), A3 => ADDR(3), D => DATA_IN(I), WCLK => CLK, WE => WE );end generate; end RAM_16X8_DISTRIBUTED_STRUCTURAL;ECE 545 – Introduction to VHDL 17ROM 16x1 (1)library IEEE;use IEEE.STD_LOGIC_1164.all;library UNISIM;use UNISIM.all;entity ROM_16X1_DISTRIBUTED is port( ADDR : in