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MASON ECE 545 - Lecture 11 ATHENa & FPGA Embedded Resources

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Slide 1ResourcesSlide 3ATHENa TeamSlide 5Why Athena?Slide 7Slide 8ATHENa Major Features (1)ATHENa Major Features (2)Generation of Results Facilitated by ATHENaSlide 12How To Start Working With ATHENa? One-Time TasksHow To Start Working With ATHENa? Repetitive Tasksdesign.config.txt Your Designdesign.config.txt Timing Formulasdesign.config.txt Application & Optimization Targetdesign.config.txt FPGA FamiliesSlide 19Library FilesLibrary Files device_lib/xilinx_device_lib.txtResult Files report_resource_utilization.txtResult Files report_timing.txtResult Files report_options.txtResult Files report_execution_time.txtdesign.config.txt Functional Simulation (1)design.config.txt Functional Simulation (2)Slide 28design.config.txt Global Genericsdesign.config.txt FPGA Family Specific GenericsSlide 31Slide 32Slide 33Basic Operations of 14 SHA-3 CandidatesSlide 35Slide 36DSP AddersSlide 38Slide 39Slide 40Slide 41DSP Adders & MultipliersBlock Memory & AddersBlock Memories used to implement T-boxes/S-boxesSlide 45Slide 46Slide 47Slide 48Slide 49Slide 50Slide 51Slide 52Slide 53Slide 54Slide 55Slide 56Slide 57Slide 58Slide 59Slide 60Slide 61Slide 62Slide 63Slide 64Generic Multiplier (1)Generic Multiplier (2)Generic Multiplier (3)Generic Multiplier (4)Slide 69Slide 70Slide 71Slide 72Slide 73Combinational and Registered MultiplierSlide 75Slide 76Slide 77Embedded Multiplier Block OverviewNumber of Embedded MultipliersMultiplier Block ArchitectureTwo Multiplier TypesMultiplier Stage3 Ways to Use Dedicated HardwareSlide 84Slide 85Slide 86Slide 87Xilinx XtremeDSPDSP48 Slice: Virtex 4Simplified Form of DSP48Choosing Inputs to DSP AdderDSP48E Slice : Virtex5New in Virtex 5 Compared to Virtex 4Slide 94Slide 95Memory TypesMemory Types in XilinxMemory Types in AlteraInference vs. InstantiationSlide 100Block RAMBlock RAM can have various configurations (port aspect ratios)Block RAM Port Aspect RatiosSingle-Port Block RAMDual-Port Block RAMBlock RAM library componentsSlide 107Slide 108Slide 109Slide 110Slide 111Slide 112Slide 113George Mason UniversityECE 545Lecture 11ATHENa & FPGA Embedded Resources2Resources•ATHENa websitehttp://cryptography.gmu.edu/athena•FPGA Embedded Resources web pageavailable from the course web page3ATHENa – Automated Tool for Hardware EvaluatioN Supported in part by the National Institute of Standards & Technology (NIST)ATHENa TeamVenkata“Vinny”MS CpEstudentEkawat“Ice”PhD CpEstudentMarcinPhD ECEstudentRajeshPhD ECEstudentMichalPhD exchangestudent fromSlovakiaJohnMS CpEstudentATHENa – Automated Tool for Hardware EvaluatioN5Benchmarking open-source tool,written in Perl, aimed at an AUTOMATED generation of OPTIMIZED results for MULTIPLE hardware platformsCurrently under development at George Mason University. http://cryptography.gmu.edu/athenaWhy Athena?6"The Greek goddess Athena was frequently called upon to settle disputes between the gods or various mortals. Athena Goddess of Wisdom was known for her superb logic and intellect. Her decisions were usually well-considered, highly ethical, and seldom motivated by self-interest.”from "Athena, Greek Goddess of Wisdom and Craftsmanship"ATHENaServerFPGA Synthesis and ImplementationResult Summary+ Database Entries23HDL + scripts + configuration files1Database EntriesDownload scripts andconfiguration files8Designer4HDL + FPGA ToolsUserDatabasequeryRanking of designs56Basic Dataflow of ATHENa0Interfaces+ Testbenches78synthesizable source filessynthesizable source filesconfiguration files configuration files testbenchtestbenchconstraint files constraint files result summary (user-friendly)result summary (user-friendly)database entries (machine- friendly)database entries (machine- friendly)ATHENa Major Features (1)•synthesis, implementation, and timing analysis in batch mode•support for devices and tools of multiple FPGA vendors: •generation of results for multiple families of FPGAs of a given vendor•automated choice of a best-matching device within a given family9ATHENa Major Features (2)•automated verification of designs through simulation in batch mode•support for multi-core processing•automated extraction and tabulation of results•several optimization strategies aimed at finding–optimum options of tools–best target clock frequency–best starting point of placementOR1011•batch mode of FPGA tools•ease of extraction and tabulation of results•Text Reports, Excel, CSV (Comma-Separated Values)•optimized choice of tool options•GMU_optimization_1 strategyGeneration of Results Facilitated by ATHENavs.12Relative Improvement of Results from Using ATHENa Virtex 5, 256-bit Variants of Hash Functions Ratios of results obtained using ATHENa suggested optionsvs. default options of FPGA toolsRead the Tutorial!Install the Required Tools(see Tutorial - Part 1 – Tools Installation)Run ATHENa_setupHow To Start Working With ATHENa?One-Time TasksDownload and unzip ATHENa http://cryptography.gmu.edu/athena/Modify design.config.txt+ possibly other configuration filesRun ATHENaHow To Start Working With ATHENa?Repetitive TasksPrepare or modify your source files& source_list.txtdesign.config.txtYour Design# directory containing synthesizable source files for the projectSOURCE_DIR = <examples/sha256_rs># A file list containing list of files in the order suitable for synthesis and implementation# low level modules first, top level entity lastSOURCE_LIST_FILE = source_list.txt# project name# it will be used in the names of result directoriesPROJECT_NAME = SHA256# name of top level entityTOP_LEVEL_ENTITY = sha256# name of top level architectureTOP_LEVEL_ARCH = rs_arch# name of clock netCLOCK_NET = clkdesign.config.txtTiming Formulas#formula for latencyLATENCY = TCLK*65#formula for throughputTHROUGHPUT = 512/(TCLK*65)design.config.txtApplication & Optimization Target# OPTIMIZATION_TARGET = speed | area | balancedOPTIMIZATION_TARGET = speed# OPTIONS = default | userOPTIONS = default# APPLICATION = single_run | exhaustive_search | placement_search | frequency_search |# GMU_Optimization_1 | GMU_Xilinx_optimization_1APPLICATION = single_run# TRIM_MODE = off | zip | deleteTRIM_MODE = zipdesign.config.txtFPGA Families# commenting the next line removes all families of XilinxFPGA_VENDOR = xilinx #commenting the next line removes a given familyFPGA_FAMILY = spartan3# FPGA_DEVICES = <list of devices> | best_match | allFPGA_DEVICES = best_matchSYN_CONSTRAINT_FILE = defaultIMP_CONSTRAINT_FILE =


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MASON ECE 545 - Lecture 11 ATHENa & FPGA Embedded Resources

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