ECE 545 Project 1 Part IV Key Scheduling Final Integration List of DeliverablesSlide 2Slide 3Slide 4Part IV due Thursday November 18, 3 PMSlide 6Slide 7Slide 8Final DeliverablesECE 545 Project 1 Part IV Key SchedulingFinal IntegrationList of DeliverablesRC5 – Key SchedulingRC5 - Key Scheduling Initialize and ConvertInitializet = 2 r + 2c = 8bwS[0] = Pwfor i=1 to t-1 do S[i] = S[i-1] + Qw Convertfor i=0 to c-1 do L[i] = 0;Copy key bits directly to the memory positions represented by L.Mixi = j = 0A = B = 0do 3 max{t, c} times { A = S[i] = (S[i] + A + B) <<< 3 B = L[j] = (L[j] + A + B) <<< (A+B) i = (i+1) mod t j = (j+1) mod c }RC5 - Key Scheduling MixPart IV due Thursday November 18, 3 PM 1. Describe a control unit of the RC5 key scheduling circuit and its interface to the memory of round keys using a block diagram and/or ASM chart.2. Translate the block diagram and the ASM chartinto synthesizable RTL VHDL code.3. Write a testbench capable of verifying the function of the designed control unit.4. Verify the correctness of your VHDL codes usingfunctional simulation, synthesis, and timing simulationfor the case of RC5 32/12/16.Encryption/decryptionunitwith control & i/o interfaceclockresetencrypt/decryptdata inputdata availabledata readmkey inputkey availablekey readkKey scheduling unitKey memorydata outputwritefullmround key(s)round numberround key(s)cycle numberFinal Integration & Reportdue Monday, November 22, 4 PM 1. Integrate together all synthesizable portions of your VHDL code describing RC5.2. Write a testbench capable of verifying the operation ofyour entire RC5 implementation.This testbench should be able to read RC5 test vectors(inputs and outputs) from a file, and generate as a resultthe messages: “circuit operating correctly” or “circuit operating incorrectly: input x, expected output y1, actual output y2”.3. Perform the functional simulation of your circuit and storetiming waveforms for a. RC5 32/12/16b. RC5 64/20/325. Synthesize and implement your entire circuit for a. RC5 32/12/16b. RC5 64/20/32Use the smallest device of the Xilinx Spartan 2 family capable of holding the bigger of the two circuits.6. For both implemented circuits, determine - maximum clock frequency - maximum encryption/decryption throughput - area in the number of CLB slices - ratio: maximum encryption/decryption throughput divided by area.7. Verify the correct operation of both versions of the RC5 circuit using timing simulation at the frequency closed to the maximum clock frequency. Store the obtained timing waveforms.Final Deliverables1. All synthesizable VHDL source codes.2. All testbenches used to verify the operation of the entire circuit and its components, including correspondinginput files containing test vectors.3. All block diagrams, state diagrams, and ASM chartsdescribing the entire circuit and its components.4. Timing waveforms demonstrating the correct operationof the entire circuit and its components.5. Final report containing the description of the•source of test vectors•any diversions from the project specification•obtained results•discussion of the encountered problems, and •issues remaining to be
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