Design of Controllers Finite State Machines and Algorithmic State Machine (ASM) ChartsRequired readingSlides based partially onSlide 4Structure of a Typical Digital SystemDatapath (Execution Unit)Controller (Control Unit)Programmable vs. Non-Programmable ControllerFinite State MachinesHardware Design with RTL VHDLSteps of the Design ProcessSteps of the Design Process Practiced in Class TodaySlide 13Finite State Machines (FSMs)Moore FSMMealy FSMSlide 17Moore MachineMealy MachineMoore vs. Mealy FSM (1)Moore vs. Mealy FSM (2)Moore FSM - Example 1Mealy FSM - Example 1Moore & Mealy FSMs – Example 1Slide 25FSMs in VHDLSlide 27Slide 28Slide 29Moore FSM in VHDL (1)Moore FSM in VHDL (2)Slide 32Mealy FSM in VHDL (1)Mealy FSM in VHDL (2)Slide 35Algorithmic State MachineElements used in ASM charts (1)State BoxDecision BoxConditional Output BoxASMs representing simple FSMsSlide 42Slide 43Slide 44Slide 45Slide 46Example 2: VHDL code (3)Slide 48ASM Chart for Mealy FSM – Example 3Slide 50Example 3: VHDL code (2)Example 3: VHDL code (3)Slide 53Slide 54Slide 55ASM Chart for Control Unit - Example 4Example 4: VHDL code (1)Example 4: VHDL code (2)Example 4: VHDL code (3)Overview on FSM2. Representation of FSMSlide 62Slide 63Slide 64State diagram and ASM chart conversionSlide 66Slide 67Slide 68Slide 69Slide 70Slide 71Slide 724. Moore vs Mealy outputSlide 74Slide 75Slide 76Slide 77VHDL Description of FSMSlide 79Slide 80Slide 81Slide 82Slide 83Slide 84Slide 85Slide 86Slide 87Slide 88Slide 89Slide 90Slide 91Simulation results for the sort operation (1) Loading memory and starting sortingSimulation results for the sort operation (2) Completing sorting and reading out memorySorting - ExamplePseudocodePseudocodeSlide 97Slide 98George Mason UniversityDesign of ControllersFinite State Machines andAlgorithmic State Machine (ASM) ChartsECE 545Lecture 122Required reading• P. Chu, RTL Hardware Design using VHDLChapter 10, Finite State Machine: Principle & PracticeChapter 11, Register Transfer Methodology: PrincipleChapter 12, Register Transfer Methodology: Practice3Slides based partially on• S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL DesignChapter 8, Synchronous Sequential Circuits Sections 8.1-8.5Chapter 8.10, Algorithmic State Machine (ASM) Charts Chapter 10.2 Design Examples4ECE 448 – FPGA and ASIC Design with VHDLDatapathvs.ControllerStructure of a Typical Digital SystemDatapath(Execution Unit)Controller(Control Unit)Data InputsData OutputsControl & Status InputsControl & Status OutputsControl SignalsStatusSignals6Datapath (Execution Unit)•Manipulates and processes data•Performs arithmetic and logic operations, shifting/rotating, and other data-processing tasks•Is composed of registers, multiplexers, adders, decoders, comparators, ALUs, gates, etc.•Provides all necessary resources and interconnects among them to perform specified task•Interprets control signals from the Controller and generates status signals for the Controller7Controller (Control Unit)•Controls data movements in the Datapath by switching multiplexers and enabling or disabling resourcesExample: enable signals for registersExample: control signals for muxes •Provides signals to activate various processing tasks in the Datapath•Determines the sequence of operations performed by the Datapath•Follows Some ‘Program’ or Schedule8Programmable vs. Non-Programmable Controller•Controller can be programmable or non-programmable•Programmable•Has a program counter which points to next instruction•Instructions are held in a RAM or ROM•Microprocessor is an example of programmable controller•Non-Programmable•Once designed, implements the same functionality•Another term is a “hardwired state machine,” or “hardwired FSM,” or “hardwired instructions”•In this course we will be focusing on non-programmable controllers.9Finite State Machines•Digital Systems and especially their Controllers can be described as Finite State Machines (FSMs)•Finite State Machines can be represented using•State Diagrams and State Tables - suitable for simple digital systems with a relatively few inputs and outputs•Algorithmic State Machine (ASM) Charts - suitable for complex digital systems with a large number of inputs and outputs•All these descriptions can be easily translated to the corresponding synthesizable VHDL codeHardware Design with RTL VHDLPseudocodeDatapath ControllerBlockdiagramBlockdiagramState diagramor ASM chartVHDL code VHDL code VHDL codeInterfaceSteps of the Design Process1. Text description2. Interface3. Pseudocode4. Block diagram of the Datapath5. Interface with the division into the Datapath and the Controller6. ASM chart of the Controller7. RTL VHDL code of the Datapath, the Controller, and the Top Unit8. Testbench of the Datapath, the Controller, and the Top Unit9. Functional simulation and debugging10. Synthesis and post-synthesis simulation11. Implementation and timing simulation12. Experimental testing1. Text description2. Interface3. Pseudocode4. Block diagram of the Datapath5. Interface with the division into the Datapath and the Controller6. ASM chart of the Controller7. RTL VHDL code of the Datapath, the Controller, and the Top Unit8. Testbench of the Datapath, the Controller, and the Top Unit9. Functional simulation and debugging10. Synthesis and post-synthesis simulation11. Implementation and timing simulation12. Experimental testingSteps of the Design ProcessPracticed in Class Today13ECE 448 – FPGA and ASIC Design with VHDLFinite State MachinesRefresher14Finite State Machines (FSMs)•Any Circuit with Memory Is a Finite State Machine•Even computers can be viewed as huge FSMs•Design of FSMs Involves•Defining states•Defining transitions between states•Optimization / minimization•Manual Optimization/Minimization Is Practical for Small FSMs Only15Moore FSM•Output Is a Function of a Present State OnlyPresent StateregisterNext StatefunctionOutputfunctionInputsPresent StateNext StateOutputsclockreset16Mealy FSM•Output Is a Function of a Present State and InputsNext StatefunctionOutputfunctionInputsPresent StateNext StateOutputsPresent Stateregisterclockreset17ECE 448 – FPGA and ASIC Design with VHDLState Diagrams18Moore Machinestate 1 /output 1state 2 /output 2transitioncondition 1transitioncondition 219Mealy Machinestate 1state 2transition condition 1 /output 1transition condition 2 /output 220Moore vs. Mealy FSM (1)•Moore