ECE 545 Project 2 SpecificationSlide 2SourcesOptimization CriteriaProject 2 - Platforms & toolsSlide 6Slide 7Slide 8Slide 9Slide 10Slide 11Slide 12Slide 13Slide 14Slide 15Slide 16Slide 17Slide 18Slide 19Slide 20Slide 21Slide 22Slide 23Project Deliverables Task 1Project Deliverables Task 2Project Deliverables Task 3Project Deliverables Task 4Project Deliverables Task 4 – cont.Slide 29Slide 30Slide 31Slide 32Slide 33Slide 34All Projects – Honor Code RulesECE 545 Project 2SpecificationProject 2 (15 points) – due Tuesday, December 19, noonApplication: cryptography OR digital signal processing optimized version with structural optimizations for minimum area and maximum throughput/area ratioTechnology: ASICTarget: revised synthesizable code scripts for Design Analyzer and PrimeTime synthesis with Design Analyzer timing analysis with PrimeTime design equivalence with FormalitySourcesSynopsys documentation and examples available at http://ece.gmu.edu/courses/ECE545/viewgraphs_F06/synopsys.htmGeorge Michael,PrimeTime: Static Timing Analysis Tool, scholarly paper,George Mason University, December 2006(available on the course web page)Optimization CriteriaMaximum ratioThroughput divided byTotal Circuit Area Architecture 2Architecture 1MinimumTotal Circuit AreaProject 2 - Platforms & toolsTarget devices: standard-cell ASICsLibraries: 90 nm TCBN90G TSMC library 130 nm TCB013GHP TSMC libraryTools:VHDL Simulation: Aldec Active HDL or ModelSimVHDL Synthesis: Synopsys Design AnalyzerTiming Analysis: Synopsys PrimeTimeDesign Equivalence: Synopsys FormalitySelect two or more versions of your synthesizable VHDL code developed as a part of Project 1 (a & b), and optimized fora) minimum areab) maximum throughput to area ratio.Use the results of your earlier experiments with FPGAsor consider multiple values of circuit parameters(such as parameter d for encryption) in order to find a circuit with the maximum throughput to area ratio.Revise your codes in such a way that they can be synthesized using Synopsys Design Analyzer with TSMC libraries of standard cells.Task 1Verify your revised codes using functional simulationbased on a comprehensive testbenchdeveloped as a part of Project 1. Task 2Prepare Design Analyzer scripts which will enable you to synthesize all considered versionsof your codes optimized for a) minimum area b) maximum throughput to area ratio.Identify commands and parameters (such as defining target clock period) that you can attempt to modify in order to obtain the synthesized circuit with a) minimum area b) maximum clock frequency c) maximum ratio of throughput to latency.Task 3Synthesize your codes using Synopsyswith the following libraries:1. Synopsys with the 90 nm TCBN90G TSMC library2. Synopsys with the 130 nm TCB013GHP TSMC libraryRepeat synthesis for multiple values of parametersidentified in Task 3, in order to find parameters leading to circuits with the a) minimum area b) maximum throughput to area ratio.Draw diagrams showing the dependence between the target clock frequency and the actual clock frequency and area.Task 4Synthesize your best codes optimized for a) minimum area b) maximum throughput to area ratiousing Synplicity Synplify Pro and the following FPGAs as target devices:1. Xilinx Spartan 32. Xilinx Virtex IIIn both cases use the smallest device of a given familycapable of holding the entire circuit with up to70% of CLB slice utilization.Task 5Compare the maximum clock frequencybetween circuits synthesized using1. Xilinx Spartan 3 FPGAvs. ASIC with 90 nm TSMC library2. Xilinx Virtex II FPGAvs.ASIC with 130 nm TSMC libraryTask 6Explain the obtained results.Prepare PrimeTime scripts to be used to analyze your circuits.Use templates suggested by George Michael andthe TA, and modify them to match your codeand the types of analyses you are planning to perform.Task 7Using PrimeTime - determine the critical paths in your circuits optimized for a) minimum area b) maximum throughput to area ratio.Mark these critical paths in your block diagram.Analyze all timing reports generated by your scriptand identify any violations of timing constraints.For the obtained violations, explain the meaning of the violation by drawing a corresponding simplified timing waveform.Task 8Using PrimeTime Repeat your analysis for the case of input and output delaysequal to the 20%,40%, 60%, and 80% of the clock period.Identify which values of input and output delayslead to violations of the timing constraints.Explain why? How would you modify your circuit toeliminate these timing violations?Task 9Using Formality, determine the design equivalence between the original VHDL code and the optimized netlist obtained from synthesis.Repeat your analysis for the circuits optimized for a) minimum area b) maximum throughput to area ratio.In case of mismatches, modify your VHDL code,resynthesize it, and check for equivalence again.When introducing changes try to follow strictlyrules for writing a synthesizable VHDL code. Task 10In case you have obtained no mismatches in Task 8without the need to modify your codes,generate the mismatches on purpose by making a smallmodification in your VHDL code and comparing it witha netlist corresponding to the unmodified code.The possible modifications may includereplacing a register by a direct connection betweenits input and output, changing the connectionsin your circuit, modifying a sensitivity list in a process, etc.Task 11Tips & Hints (1)Each entity and each package should be placedin a different file.The name of each file should be exactly the sameas the name of an entity or package it contains.Arrange entity names in the bottom-up order(the top-most entity at the end of the list)and define this list in your script using the commandblocks = { entity1, entity2, …, entityN}Tips & Hints (2)Use only one clock in your entire design.Use an identical name for the clock signal in all yourentities and packages (including declarationsof components).Use the same clock name in all clock-related commandsof your script, such as create_clock, set_clock_transition, etc.Avoid advanced features, such as:• multiple clocks, • gated clocks, • multicycle paths, • circular feedback loops containing only combinational logic.Although these features are supported by Synopsys,their correct use requires additional