# MASON ECE 545 - Lecture 10 Variables, Attributes, Functions and Procedures, Data Types (105 pages)

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## Lecture 10 Variables, Attributes, Functions and Procedures, Data Types

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## Lecture 10 Variables, Attributes, Functions and Procedures, Data Types

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Lecture Notes

Pages:
105
School:
George Mason University
Course:
Ece 545 - Digital System Design with VHDL
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Unformatted text preview:

ECE 545 Lecture 10 Variables Attributes Functions and Procedures Data Types ECE 545 Introduction to VHDL George Mason University Resources Volnei A Pedroni Circuit Design with VHDL Chapter 7 Signals and Variables Chapter 11 Functions and Procedures Sundar Rajan Essential VHDL RTL Synthesis Done Right Chapter 11 Scalable and Parameterizable Design Chapter 12 Enhancing Design Readability and Reuse ECE 545 Introduction to VHDL 2 Combinational Logic Synthesis for Intermediates ECE 545 Introduction to VHDL 3 2 to 4 Decoder En w w 1 0 y y y y 0 1 2 3 1 0 0 1 0 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 0 1 1 1 0 0 0 1 0 x x 0 0 0 0 a Truth table ECE 545 Introduction to VHDL w 0 w 1 En y 0 y 1 y 2 y 3 b Graphical symbol 4 VHDL code for a 2 to 4 Decoder LIBRARY ieee USE ieee std logic 1164 all ENTITY dec2to4 IS PORT w IN En IN y OUT END dec2to4 STD LOGIC VECTOR 1 DOWNTO 0 STD LOGIC STD LOGIC VECTOR 3 DOWNTO 0 ARCHITECTURE dataflow OF dec2to4 IS SIGNAL Enw STD LOGIC VECTOR 2 DOWNTO 0 BEGIN Enw En w WITH Enw SELECT y 0001 WHEN 100 0010 WHEN 101 0100 WHEN 110 1000 WHEN 111 0000 WHEN OTHERS END dataflow ECE 545 Introduction to VHDL 5 Describing combinational logic using processes LIBRARY ieee USE ieee std logic 1164 all ENTITY dec2to4 IS PORT w IN En IN y OUT END dec2to4 STD LOGIC VECTOR 1 DOWNTO 0 STD LOGIC STD LOGIC VECTOR 0 TO 3 ARCHITECTURE Behavior OF dec2to4 IS BEGIN PROCESS w En BEGIN IF En 1 THEN CASE w IS WHEN 00 WHEN 01 WHEN 10 WHEN OTHERS END CASE ELSE y 0000 END IF END PROCESS END Behavior ECE 545 Introduction to VHDL y 1000 y 0100 y 0010 y 0001 6 Describing combinational logic using processes LIBRARY ieee USE ieee std logic 1164 all ENTITY seg7 IS PORT bcd IN STD LOGIC VECTOR 3 DOWNTO 0 leds OUT STD LOGIC VECTOR 1 TO 7 END seg7 ARCHITECTURE Behavior OF seg7 IS BEGIN PROCESS bcd BEGIN CASE bcd IS abcdefg WHEN 0000 leds 1111110 WHEN 0001 leds 0110000 WHEN 0010 leds 1101101 WHEN 0011 leds 1111001 WHEN 0100 leds 0110011 WHEN 0101 leds 1011011 WHEN 0110 leds 1011111 WHEN 0111 leds

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