Variables, Attributes, Functions and Procedures, Data TypesResourcesSlide 32-to-4 DecoderVHDL code for a 2-to-4 DecoderDescribing combinational logic using processesSlide 7Slide 8Incorrect code for combinational logic - Implied latch (1)Incorrect code for combinational logic - Implied latch (2)Slide 11Covering all cases in the IF statementCovering all cases in the CASE statementSlide 14Advanced VHDL for synthesisSlide 16Variable – Example (1)Variable – Example (2)Variables - featuresSlide 20Variable – ExampleIncorrect Code using SignalsN-bit NANDN-bit NAND architecture using variablesIncorrect N-bit NAND architecture using signalsCorrect N-bit NAND architecture using signalsSlide 27Parity generator entityParity generator architecture using signalsParity generator architecture using variablesSlide 31For BeginnersSlide 33For IntermmediatesSlide 35One-dimensional arrays – Examples (1)One-dimensional arrays – Examples (2)Slide 38Predefined Unconstrained Array TypesSlide 40User-defined Unconstrained Array TypesSlide 42Array AttributesArray Attributes - ExamplesSlide 45SubprogramsTypical locations of subprogramsSlide 48Functions – basic featuresFunction syntaxFunction parameters - exampleFunction calls - examplesFunction – Example 1Function call – Example 1Function – Example 2Slide 56Package containing a function (1)Package containing a function (2)Type conversion function (1)Type conversion function (2)Type conversion function (3)Slide 62Procedures – basic featuresProcedure syntaxProcedure parameters - exampleProcedure calls - examplesProcedure – example (1)Procedure – example (2)Slide 69Operator as a function (1)Operator as a function (2)Slide 72Operator overloadingDifferent declarations for the same operator - ExampleSlide 75Slide 76Notion of typeExample of strong typingSlide 79Classification of data typesSlide 81Integer typeUser defined integer types - ExamplesSlide 84Predefined enumeration types (1)Predefined enumeration types (2)User-defined enumeration types - ExamplesSlide 88Floating point typesReal literals - examplesThe ANSI/IEEE standard floating-point number representation formatsUser-defined floating-point types - ExamplesSlide 93Attributes of all scalar typesAttributes of all scalar types - examplesAttributes of discrete typesAttributes of discrete types - examplesSlide 98SubtypePredefined subtypesUser-defined subtypes - ExamplesSlide 102Operators (1)Operators (2)Operators (3)ECE 545 – Introduction to VHDL George Mason UniversityVariables, Attributes, Functions and Procedures,Data TypesECE 545Lecture 10ECE 545 – Introduction to VHDL 2Resources• Volnei A. Pedroni, Circuit Design with VHDLChapter 7, Signals and VariablesChapter 11, Functions and Procedures• Sundar Rajan, Essential VHDL: RTL Synthesis Done Right Chapter 11, Scalable and Parameterizable Design Chapter 12, Enhancing Design Readability and ReuseECE 545 – Introduction to VHDL 3Combinational Logic Synthesisfor IntermediatesECE 545 – Introduction to VHDL 42-to-4 Decoder0 0 1 1 1 0 1 y 0 w 1 0 w 0 x x 1 1 0 1 1 En0 0 0 1 0 y 1 1 0 0 0 0 y 2 0 1 0 0 0 y 3 0 0 1 0 0 w 0 Eny 0 w 1 y 1 y 2 y 3 (a) Truth table (b) Graphical symbolECE 545 – Introduction to VHDL 5VHDL code for a 2-to-4 DecoderLIBRARY ieee ;USE ieee.std_logic_1164.all ;ENTITY dec2to4 ISPORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;En : IN STD_LOGIC ;y : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;END dec2to4 ;ARCHITECTURE dataflow OF dec2to4 ISSIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO 0) ;BEGINEnw <= En & w ;WITH Enw SELECTy <= “0001" WHEN "100","0010" WHEN "101","0100" WHEN "110",“1000" WHEN "111","0000" WHEN OTHERS ;END dataflow ;ECE 545 – Introduction to VHDL 6Describing combinational logic using processesLIBRARY ieee ;USE ieee.std_logic_1164.all ;ENTITY dec2to4 ISPORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;En : IN STD_LOGIC ;y : OUT STD_LOGIC_VECTOR(0 TO 3) ) ;END dec2to4 ;ARCHITECTURE Behavior OF dec2to4 ISBEGINPROCESS ( w, En )BEGINIF En = '1' THENCASE w ISWHEN "00" => y <= "1000" ;WHEN "01" => y <= "0100" ;WHEN "10" => y <= "0010" ;WHEN OTHERS => y <= "0001" ;END CASE ;ELSEy <= "0000" ;END IF ;END PROCESS ;END Behavior ;ECE 545 – Introduction to VHDL 7Describing combinational logic using processesLIBRARY ieee ;USE ieee.std_logic_1164.all ;ENTITY seg7 ISPORT ( bcd : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;leds : OUT STD_LOGIC_VECTOR(1 TO 7) ) ;END seg7 ;ARCHITECTURE Behavior OF seg7 ISBEGINPROCESS ( bcd )BEGINCASE bcd IS -- abcdefgWHEN "0000" => leds <= "1111110" ;WHEN "0001" => leds <= "0110000" ;WHEN "0010" => leds <= "1101101" ;WHEN "0011" => leds <= "1111001" ;WHEN "0100" => leds <= "0110011" ;WHEN "0101" => leds <= "1011011" ;WHEN "0110" => leds <= "1011111" ;WHEN "0111" => leds <= "1110000" ;WHEN "1000" => leds <= "1111111" ;WHEN "1001" => leds <= "1110011" ;WHEN OTHERS => leds <= "-------" ;END CASE ;END PROCESS ;END Behavior ;ECE 545 – Introduction to VHDL 8Describing combinational logic using processesLIBRARY ieee ;USE ieee.std_logic_1164.all ;ENTITY compare1 ISPORT ( A, B : IN STD_LOGIC ;AeqB : OUT STD_LOGIC ) ;END compare1 ;ARCHITECTURE Behavior OF compare1 ISBEGINPROCESS ( A, B )BEGINAeqB <= '0' ;IF A = B THENAeqB <= '1' ;END IF ;END PROCESS ;END Behavior ;ECE 545 – Introduction to VHDL 9Incorrect code for combinational logic- Implied latch (1)LIBRARY ieee ;USE ieee.std_logic_1164.all ;ENTITY implied ISPORT ( A, B : IN STD_LOGIC ;AeqB : OUT STD_LOGIC ) ;END implied ;ARCHITECTURE Behavior OF implied ISBEGINPROCESS ( A, B )BEGINIF A = B THENAeqB <= '1' ;END IF ;END PROCESS ;END Behavior ;ECE 545 – Introduction to VHDL 10Incorrect code for combinational logic- Implied latch (2)A B AeqBECE 545 – Introduction to VHDL 11Describing combinational logic using processesRules that need to be followed:1. All inputs to the combinational circuit should be included in the sensitivity list2. No other signals should be included in the sensitivity list3. None of the statements within the process should be sensitive to rising or falling edges4. All possible cases need to be covered in the internalIF and CASE statements in order to avoid implied latchesECE 545 – Introduction to VHDL 12Covering all cases in the IF statementUsing ELSEUsing default valuesAeqB <= '0' ;IF A = B THENAeqB <= '1' ;IF A = B THENAeqB <= '1' ; ELSEAeqB <= '0' ;ECE 545 – Introduction to VHDL 13Covering all cases in the CASE statementUsing WHEN OTHERSUsing default