Program Development EnvironmentsAcknowledgementsSlide 3Slide 4Slide 5SRC Compilation ProcessSlide 7Slide 8Cray XD1 Programming FlowsXtreme DSP Design FlowHDL-based SGI Altix Programming FlowHLL-based SGI Altix Programming FlowCompiling A Mitrion ProgramThe Mitrion PlatformA New Processor Architecture Specifically For FPGAsProcessor Architecture: A Cluster-On-A-ChipSlide 17A C-family LanguageTypesLanguage constructsSlide 21Compiler, Simulator And DebuggerSlide 23Slide 24Slide 25Slide 26Slide 27Structure of the SRC macro repositoryFiles describing an SRC macroSlide 30Slide 31Slide 32Slide 33Slide 34Slide 35Slide 36Hyperspectral Dimension Reduction (Techniques)Discrete Wavelet Transform (DWT) Decomposition (Mallat Algorithm)Wavelet-Based Dimension Reduction (Description)Slide 40Slide 41Slide 42Slide 43Slide 44Overlapping Data Transfer with Computation (SRC-6)Streams (SRC-6)Cray XD-1Slide 48Slide 49Slide 50Slide 51Slide 52Slide 53Streaming (SGI-Altix)DWT Decomposition (One Engine  One FPGA)DWT Decomposition (cnt’d) (Cray-XD1)Slide 57Slide 58Slide 59Slide 60Slide 61Encryption on SRC-6 – No streaming encryption.mc (1)encrypt_decrypt = 0; nbytes = MAX_OBM_SIZE * 8*3; start_timer(); read_timer(&t1); DMA_CPU(CM2OBM, S1OBM, MAP_OBM_stripe(1,"A,B,C"), sdata, 1, nbytes, 0); wait_DMA(0); read_timer(&t2); for(i=0;i<MAX_OBM_SIZE;i++) { des (S1OBM[i], key, encrypt_decrypt, &S4OBM[i]); des (S2OBM[i], key, encrypt_decrypt, &S5OBM[i]); des (S3OBM[i], key, encrypt_decrypt, &S6OBM[i]); } read_timer(&t3);Encryption on SRC-6 – No streaming encryption.mc (3)Encryption on SRC-6 – No streaming des_blkbx.vEncryption on SRC-6 – No streaming des.info (1)Encryption on SRC-6 – No streaming des.info (2)Encryption on SRC-6 - with streaming encryption.mc (1)start_timer(); read_timer(&t1); #pragma src parallel sections { #pragma src section { stream_dma_cpu_dual (&S0, &S1, PORT_TO_STREAM, S1OBM, DMA_A_B, sdata, 1, nbytes); } #pragma src section { for (i=0; i<MAX_OBM_SIZE; i++) { get_stream (&S0, &v0); get_stream (&S1, &v1); des (v0, key, encrypt_decrypt, &S4OBM[i]); des (v1, key, encrypt_decrypt, &S5OBM[i]); }; } }Encryption on SRC-6 – with streaming encryption.mc (3)Slide 71Slide 72Slide 73Slide 74Slide 75Slide 76Secret-key cipher breakingSlide 78Slide 79Slide 80Slide 81Slide 82Slide 83Slide 84Slide 85Slide 86Slide 87Slide 88Slide 89Slide 90Slide 91Slide 92Slide 93Slide 94Slide 95Slide 96Slide 97Timing MeasurementsResults (Latency)Slide 100Slide 101Slide 102Slide 103Slide 104Slide 105The application: Thin Plate Splines - image analysis of protein gelsHost Program - running on Opteron CPU, calling FPGA subroutineFPGA program (1/3) - accelerated subroutine in Mitrion-cFPGA program (2/3) - accelerated subroutine in Mitrion-cFPGA program (3/3) - accelerated subroutine in Mitrion-cSlide 111Slide 112Slide 113Slide 114Slide 115Slide 116Slide 117Slide 118Slide 119Slide 120Slide 121Slide 122Slide 123Slide 124FPGA Mapping in VIVA TMSlide 126Slide 127Slide 128FPGA-FPGA Data Transfer in VIVA TMSlide 130Slide 131Using On-Chip Memory (OCM) in VIVATMSlide 133Slide 134Run-time Reconfiguration in VIVATMIdeal Program EntryActual Program EntrySlide 138Slide 139MAP Board ExecutionMAP Emulator + DFG SimulatorMAP Emulator + Verilog SimulatorX86 System in VIVATMSlide 144Debugging in VIVATMDebugging in the SGI EnvironmentSlide 147Slide 148Slide 149Slide 150Slide 151Slide 1521Program Development EnvironmentsProgram Development EnvironmentsLanguages & ToolsLanguages & ToolsKris GajGeorge Mason University2AcknowledgementsAMICrayMitrionNCSASGISRCStar BridgeDoD/LUCITECompanies, centers, and sponsors3• Esmail Chitalwala (GWU/Star Bridge)• Hatim Diab (GWU)• Esam El-Araby (GWU)• Miaoqing Huang (GWU)• Allen Michalski (GMU/USC)• Nandkishore Sastry (GMU)• Chang Shu (GMU)• Mohamed Taher (GWU)• Proshanta Saha (GWU)AcknowledgementsGWU/GMU studentsC function for P C function for MAPVHDLmacro SRC Program PartitioningP systemFPGA systemHLLHDLMain C programfor P Function_1(a, d, e)Function_2(d, e, f)Function_1Function_2Macro_1(a, b, c)Macro_2(b, d)Macro_2(c, e)Macro_3(s, t)Macro_1(n, b)Macro_4(t, k)FPGA………………Macro_1Macro_2Macro_2abcd eFPGA contents afterFunction_1 callRole of the three program componentsC functions for MAPSRC Compilation ProcessObjectfilesApplication sourcesMacro sources MAP CompilerP CompilerLogic synthesisPlace & RouteLinker.v files.bin files.ngo files.o files .o filesApplicationexecutableConfigurationbitstreamsHDLsourcesNetlists.c or .f files.vhd or .v filesLogic synthesisPlace & RouteLinker.v files.bin files.ngo filesHDLsources. or.mc or .mf filesLibraryObjectSheetsStarStar Bridge Programming Environment - VivaPlace & Route.bin files.ngo filesApplicationexecutableConfigurationbitstreamsNetlistsStar Bridge Compilation ProcessVIVAGraphical User InterfaceUser inputXilinxCray XD1 Programming FlowsSource: [Cray, MAPLD05]Synthesisprocess (a, m) isbegin z <= a and m;end process;int mask(a, m){return (a & m);}VHDL/Verilog SynthesisMitrion-CVHDL,VerilogMentor GraphicsSynopsysSynplicityXilinxamz01001011010101010101101010010100010101101010100101010101MATLAB/SimulinkThe MathWorksStandardFlowMitrionHigh-levelFlowSystemGeneratorXilinxXilinxPlace & RouteGate-level EDIF VHDL or VerilogXtreme DSP Design FlowHDL-based SGI Altix Programming Flow IA-32 Linux MachineDesign iterationsDesign Entry(Verilog, VHDL)Design Synthesis(Synplify Pro, Amplify)Design Implementation(ISE)Design VerificationBehavioral Simulation(VCS, Modelsim)Static Timing Analysis(ISE Timing Analyzer).v, .vhd.v, .vhd.edf.ncd, .pcf.binMetadataProcessing(Python).v, .vhd.cfgAltix Device Programming(RASC Abstraction Layer, Device Manager, Device Driver)Real-time Verification(gdb).cIA-32 Linux MachineRTL Generation and Integration with Core ServicesDesign Synthesis(Synplify Pro, Amplify)Design VerificationBehavioral Simulation(VCS, Modelsim)Static Timing Analysis(ISE Timing Analyzer).v, .vhd.v, .vhd.edf.ncd, .pcf.binMetadataProcessing(Python).v, .vhd.cfgAltix Device Programming(RASC Abstraction Layer, Device Manager, Device Driver)Real-time Verification(gdb).cDesign Implementation(ISE)HLL Design Entry(Handel-C, Mitrion C, Viva)HLL-based SGI Altix Programming FlowCompiling A Mitrion ProgramProcessorConfiguratorProcessorArchitectureMitrion-CSource codeProcessorHW-Design(VHDL IP Core)FPGAMitrion Software Development KitSimulator& DebuggerProcessorMachine-codeCompilerThe Mitrion Platform1) The Mitrion Virtual Processor–A