Algorithmic State Machines Advanced TestbenchesSources & Required ReadingSlide 3Algorithmic State MachineElements used in ASM charts (1)Elements used in ASM charts (2)Elements used in ASM charts (3)Slide 8Slide 9Slide 10ASM Chart for Mealy FSM – Example 2Slide 12Slide 13Slide 14ASM Chart for Control Unit - Example 3Slide 16Pseudocode for the sort operationStructure of a Typical Digital SystemHardware Design with RTL VHDLVHDL code (1) – Entity declarationPackage components (1)Package components (2)VHDL code (2) – Datapath signal declarationsVHDL code (3) – Control unit signal declarationsVHDL code (4) - DatapathVHDL code (5) - DatapathVHDL code (6) – Control Unit Part 1VHDL code (7) – Control Unit Part 1VHDL code (8) – Control Unit Part 2VHDL code (9) – Control Unit Part 2VHDL code (10) – Control Unit Part 2Simulation results for the sort operation (1) Loading the registers and starting sortingSimulation results for the sort operation (2) Completing sorting and reading out registersSlide 34Slide 35Testbench (1)Testbench (2)Testbench (3)Testbench (4)Testbench (5)Slide 41Design Under Test (1)Design Under Test (2)Test vector file (1)Test vector file (2)Slide 46Slide 47Slide 48Slide 49Slide 50Testbench (6)Testbench (7)Hex formatECE 545 – Introduction to VHDL George Mason UniversityAlgorithmic State MachinesAdvanced TestbenchesECE 545Lecture 6ECE 545 – Introduction to VHDL 2Sources & Required Reading•Stephen Brown and Zvonko Vranesic,Fundamentals of Digital Logic with VHDL Design Chapter 8.10Algorithmic State Machine (ASM) ChartsChapter 10.2.6Sort Operation (handouts distributed in class)ECE 545 – Introduction to VHDL 3Algorithmic State Machine (ASM)ChartsECE 545 – Introduction to VHDL 4Algorithmic State MachineAlgorithmic State Machine – representation of a Finite State Machine suitable for FSMs with a larger number of inputs and outputs compared to FSMs expressed using state diagrams and state tables.ECE 545 – Introduction to VHDL 5Elements used in ASM charts (1)Output signalsor actions(Moore type)State nameCondition expression0 (False) 1 (True)Conditional outputs or actions (Mealy type) (a) State box (b) Decision box(c) Conditional output boxECE 545 – Introduction to VHDL 6Elements used in ASM charts (2)•State box – represents a state. Equivalent to a node in a state diagram or a row in a state table.Moore type outputs are listed inside of the box. It is customary to write only the name of the signal that has to be asserted in the given state, e.g., z instead of z=1. Also, it might be useful to write an action to be taken, e.g., Count = Count + 1, and only later translate it to asserting a control signal that causes a given action to take place.ECE 545 – Introduction to VHDL 7Elements used in ASM charts (3)•Decision box – indicates that a given condition is to be tested and the exit path is to be chosen accordinglyThe condition expression consists of one or more inputs to the FSM.•Conditional output box – denotes output signals that are of the Mealy type. The condition that determines whether such outputs are generated is specified in the decision box.ECE 545 – Introduction to VHDL 8Moore FSM – Example 1: State diagramC z 1 = Reset B z 0 = A z 0 = w 0 = w 1 = w 1 = w 0 = w 0 = w 1 =ECE 545 – Introduction to VHDL 9w w w 0 1 0 1 0 1 A B C z Reset w w w 0 1 0 1 0 1 A B C z Reset ASM Chart for Moore FSM – Example 1ECE 545 – Introduction to VHDL 10A w 0 = z 0 = w 1 = z 1 = B w 0 = z 0 = Reset w 1 = z 0 = Mealy FSM – Example 2: State diagramECE 545 – Introduction to VHDL 11ASM Chart for Mealy FSM – Example 2w w 0 1 0 1 A B Reset zECE 545 – Introduction to VHDL 12Control Unit Example: Arbiter (1)Arbiterresetr1r2r3g1g2g3clockECE 545 – Introduction to VHDL 13Idle000 1xx Reset gnt1 g 1 1 = x1x gnt2 g 2 1 = xx1 gnt3 g 3 1 = 0xx 1xx 01x x0x 001 xx0 Control Unit Example: Arbiter (2)ECE 545 – Introduction to VHDL 14Control Unit Example: Arbiter (3)r 1 r 2 r 1 r 2 r 3 IdleReset gnt1 g 1 1 = gnt2 g 2 1 = gnt3 g 3 1 = r 1 r 1 r 1 r 2 r 3 r 2 r 3 r 1 r 2 r 3 r 1 r 2 r 1 r 2 r 3 IdleReset gnt1 g 1 1 = gnt2 g 2 1 = gnt3 g 3 1 = r 1 r 1 r 1 r 2 r 3 r 2 r 3 r 1 r 2 r 3ECE 545 – Introduction to VHDL 15ASM Chart for Control Unit - Example 3r 1 r 3 0 1 1 IdleReset r 2 r 1 r 3 r 2 gnt1gnt2gnt31 1 1 0 0 0 g 1 g 2 g 3 0 0 1 r 1 r 3 0 1 1 IdleReset r 2 r 1 r 3 r 2 gnt1gnt2gnt31 1 1 0 0 0 g 1 g 2 g 3 0 0 1ECE 545 – Introduction to VHDL 16SortingECE 545 – Introduction to VHDL 17Pseudocode for the sort operationfor i = 0 tok 2 doA = R i ; for j = i + 1 tok 1 doB = R j ; ifB < A thenR i = B ; R j = A ; A = R i ; end if ; end for; end for; ––ECE 545 – Introduction to VHDL 18Structure of a Typical Digital SystemExecution Unit(Datapath)Control Unit(Control)Data InputsData OutputsControl InputsControl OutputsControl SignalsECE 545 – Introduction to VHDL 19Hardware Design with RTL VHDLPseudocodeExecution Unit Control UnitBlockdiagramBlockdiagramASMVHDL code VHDL code VHDL codeECE 545 – Introduction to VHDL 20VHDL code (1) – Entity declarationLIBRARY ieee;USE ieee.std_logic_1164.all;USE work.components.all ;ENTITY sort ISGENERIC ( N : INTEGER := 4 ) ;PORT (Clock, Resetn : IN STD_LOGIC ;s, WrInit, Rd : IN STD_LOGIC ;DataIn : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;RAdd : IN INTEGER RANGE 0 TO 3 ;DataOut : BUFFER STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;Done : BUFFER STD_LOGIC ) ;END sort ;ECE 545 – Introduction to VHDL 21Package components (1)LIBRARY ieee ;USE ieee.std_logic_1164.all ;PACKAGE components IS-- n-bit register with enable COMPONENT regne GENERIC ( N : INTEGER := 4 ) ;PORT ( R : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;Resetn : IN STD_LOGIC ;E : IN STD_LOGIC ;Clock : IN STD_LOGIC ;Q : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ; END COMPONENT ;ECE 545 – Introduction to VHDL 22Package components (2)-- up-counter that counts from 0 to modulus-1 COMPONENT upcount GENERIC ( modulus : INTEGER := 8 ) ;PORT ( Resetn : IN STD_LOGIC ;Clock : IN STD_LOGIC ;E : IN STD_LOGIC ;L : IN STD_LOGIC ;R : IN INTEGER RANGE 0 TO modulus-1 ;Q : BUFFER INTEGER RANGE 0 TO modulus-1 ) ; END COMPONENT ;END components ;ECE 545 – Introduction to VHDL 23VHDL code (2) – Datapath signal declarationsARCHITECTURE Dataflow OF sort IS-- datapath data busesTYPE RegArray IS