ECE 545 Project 1 Specification Part IIPhase 2, due Thursday October 21, noonSlide 3Slide 4Slide 5Slide 6Slide 7Slide 8ECE 545 Project 1Specification Part IIPhase 2, due Thursday October 21, noon 1. Draw a state diagram of the control unit that governs the operation of the encryption/decryption unit and the input/output interface.2. Describe the designed control unit using synthesizable VHDL code.3. Write a testbench capable of verifying function of your control unit.4. Write a testbench capable of verifying operation of the entire circuit composed of the •encryption/decryption unit, •control unit, and •input/output interface. This testbench should read test vectors from a file.5. Synthesize and implement your circuit for RC5 32/12/16 using the smallest device of the Xilinx Spartan 2 family capable of holding the entire circuit.6. For the entire implemented circuit, determine• maximum clock frequency• maximum encryption/decryption throughput• area in number of CLB slices• ratio: maximum encryption/decryption throughput divided by area.7. Verify the correct operation of your circuit using timing simulation at the frequency closed to the maximum clock frequency.RC5 w/r/bw - word size in bitsinput/output block size, m = 2 words = 2w bits Typical values: w=32 64-bit input/output block w=64 128-bit input/output blockr - number of roundsb - key size in byteskey size in bits, k = 8b bits 0 b 255w = 16, 32, 64keyschedulingencryption/decryptionunitmemory of round keysoutputinputinput interfaceoutput interfacecontrol unitinput controlImplementation of a secret-key cipherRound keys precomputedkeyoutput controlEncryption/decryptionunitwith control & i/o interfaceclockresetencrypt/decryptdata inputdata availabledata readmkey inputkey availablekey readkKey scheduling unitKey memorydata outputwritefullmround key(s)round numberround key(s)cycle numberregistercombinationallogicone roundmultiplexerBasic iterative architectureround keyEncrypt/DecryptInitial transformationFinal transformationr timesRound Key[i]i:=i+1Round Key[0]i:=1i < rCipher RoundRound Key[#rounds+1]Typical Flow Diagram of a Secret-Key Block
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